AHIP6+ Manual
3-8
Advanced Chipset Control Submenu
Xycom BIOS Setup Utility
Advanced
Advanced Chipset Control
Item Specific Help
Enable Memory Gap
[Disabled]
If the item you
ECC Config:
[Disabled]
are viewing has
SERR Signal Condition:
[Multiple bit]
specific help, it will
8-bit I/O Recovery:
[3.5]
be listed here.
16-bit I/O Recovery:
[3.5]
F1
Help
¯
Select Item
-/+
Change Values
F9
Setup Defaults
ESC
Exit
¨
Select Menu
Enter Select » Submenu
F10 Save & Exit
Figure 3-7. Advanced Chipset Control Submenu
This menu allows you to change the values in the chipset registers and
optimize your system’s performance.
Note
Most system configurations will work best with these options in their de-
fault configurations. Fast processors (e.g., a 450 MHz Pentium II proces-
sor) may cause I/O failures at the default recovery values. You can in-
crease the number of cycles when encountering this problem; however,
slowing down the clock too much may cause I/O initialization problems.
You should increase the number of clock cycles incrementally, until you
see an improvement in I/O performance.
Table 3-7. Advanced Chipset Control Submenu Options
Option
Description
Enable Memory Gap
Allows creation at a 128K memory gap in conventional memory from 512K to 640K, or a
1MB memory gap in extended memory from 15 MB to 16 MB. Requires use of conven-
tional or extended memory. Default is [Disabled].
ECC Configuration
Allows configuration of Error Checking and Correction Memory. Requires ECC mem-
ory. Default is [Disabled]
SERR Signal Conditions
Allows configuration of conditions upon which the SERR signal is to be asserted for
ECC memory. Requires ECC memory. Default is [Multiple bit].
8-bit I/O Recovery
16-bit I/O Recovery
Number of ISA clock cycles inserted between back-to-back I/O operations.
