XTAG-2 Hardware Manual (1.0)
6
I/O Port-to-Pin Mapping
The table below provides a full description of the port-to-pin mappings described
throughout this document.
Pin
Port
Processor
1b
4b
8b
X0D0
P1A0
TDSRC
X0D1
P1B0
TDSNK
X0D2
P4A0
P8A0
X0D3
P4A1
P8A1
X0D4
P4B0
P8A2
XL1_UP1
X0D5
P4B1
P8A3
XL1_UP0
X0D6
P4B2
P8A4
XL1_DN0
X0D7
P4B3
P8A5
XL1_DN1
X0D8
P4A2
P8A6
X0D9
P4A3
P8A7
X0D10
P1C0
TMS
X0D11
P1D0
TCK
X0D12
P1E0
ULPI_STP
X0D13
P1F0
ULPI_NXT
X0D14
P4C0
P8B0
ULPI_DATA[0:7]
X0D15
P4C1
P8B1
X0D16
P4D0
P8B2
X0D17
P4D1
P8B3
X0D18
P4D2
P8B4
X0D19
P4D3
P8B5
X0D20
P4C2
P8B6
X0D21
P4C3
P8B7
X0D22
P1G0
ULPI_DIR
X0D23
P1H0
ULPI_CLK
X0D24
P1I0
PHY_RST_N
X0D25
P1J0
UART_RX
X0D26
P4E0
UART_TX
X0D27
P4E1
X0D32
P4E2
X0D33
P4E3
X0D34
P1K0
DEBUG
X0D35
P1L0
TRST_N
X0D36
P1M0
RST_N
X0D37
P1N0
X0D38
P1O0
X0D39
P1P0
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