XMOS xCORE-200 Multi-channel Audio board, Руководство по конструкции

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USB Audio Design Guide 82/110
· S/PDIF Transmitter
·
MIDI
The software layout is the identical to the dual tile L-Series Multi-channel Reference
Design and therefore the diagram Figure 37 shows the software arrangement of
the code running on the xCORE-200 device.
As with the L/U-Series, each unit runs in a single core concurrently with the others
units. The lines show the communication between each functional unit.
6.6.1 Clocking and Clock Selection
The board includes two options for master clock generation:
· A single oscillator with a Phaselink PLL to generate fixed 24.576MHz and
22.5792MHz master-clocks
· A Cirrus Logic CS2100 clock multiplier allowing the master clock to be generated
from a XCore derived reference.
The master clock source is controlled by a mux which, in turn, is controlled by bit
5 of PORT 8C :
Value Source
0 Master clock is sourced from PhaseLink PLL
1 Master clock is source from Cirrus Clock Multiplier
Figure 40:
Master Clock
Source
Selection
The clock-select from the phaselink part is controlled via bit 7 of PORT 8C :
Value Frequency
0 24.576MHz
1 22.579MHz
Figure 41:
Master Clock
Frequency
Select
6.6.2 DAC and ADC Configuration
The board is equipped with a single multi-channel audio DAC (Cirrus Logic CS4384)
and a single multi-channel ADC (Cirrus Logic CS5368) giving 8 channels of analogue
output and 8 channels of analogue input.
Configuration of both the DAC and ADC takes place using I2C. The design uses
the I2C component sc_i2c
30
.
The reset lines of the DAC and ADC are connected to bits 1 and 6 of PORT 8C
respectively.
30
http://www.github.com/xcore/sc_i2c
XM0088546.1