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Appendix B

Default Jumper Settings

The following table lists the jumpers that must be installed on the ZCU1285 board for proper
operation. These jumpers must be installed except where specifically noted in this user guide.

IMPORTANT! Any jumper not listed in the following table should be left open for normal operation.

Table 28: Default Jumper Settings

Reference

Designator

Name

Board Location

Jumper/DIP-Switch

Position

Comments

SW2.2

VCCINT

Upper left

ENABLED

SW2.3

VCCAUX

Upper left

ENABLED

SW2.4

VCCBRAM

Upper left

ENABLED

SW2.5

VCCO_HP

Upper left

ENABLED

SW2.6

VCCO_HD

Upper left

ENABLED

SW2.7

VCCPINT

Upper left

ENABLED

SW2.8

VCCPAUX

Upper left

ENABLED

SW2.9

VCC_PSPLL

Upper left

ENABLED

SW2.10

VCCO_DDR

Upper left

ENABLED

SW2.11

VCCO_MIO

Upper left

ENABLED

SW2.12

VCCINT_AMS

Upper left

ENABLED

J87

GTY PMBUS CTRL

Upper left

GND (2-3)

J215

PMBUS CTRL

Center Left

GND (2-3)

J40

POR_OVERRIDE

Center middle

GND (2-3)

J121

DUT I2C

Upper right

GND (2-3) DIS

Disabled

J125

SYS I2C

Upper right

PWR (1-2) EN

Enabled

J154

GTY PMBUS ISO

Upper right

Installed

PMBUS ISO

Upper right

Installed

J165

PS Mode Pin 0

Upper right

GND (2-3)

JTAG mode

J166

PS Mode Pin 1

Upper right

GND (2-3)

JTAG mode

J164

PS Mode Pin 2

Upper right

GND (2-3)

JTAG mode

J163

PS Mode Pin 3

Upper right

GND (2-3)

JTAG mode

J275

VTT_HP SOURCE

Upper right

VTT_HP (1-2)

J216

VTT_HD SOURCE

Lower Right

VTT_HD (1-2)

J60

APM PMBUS CTRL

Center Right

Installed

J11

CLK_DIFF_1_P

Lower Middle

Installed

Appendix B: Default Jumper Settings

UG1348 (v1.0) July 16, 2019

www.xilinx.com

ZCU1285 Board User Guide

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Содержание ZCU1285

Страница 1: ...ZCU1285 Characterization Board User Guide UG1348 v1 0 July 16 2019...

Страница 2: ...lowing table shows the revision history for this document Section Revision Summary 07 16 2019 Version 1 0 Initial release N A Revision History UG1348 v1 0 July 16 2019 www xilinx com ZCU1285 Board Use...

Страница 3: ...verters and Sampling Clocks 28 Serial Transceivers and Reference Clocks 32 SuperClock 2 Module 37 SuperClock RF2 Module 38 Balun Board 41 FPGA Mezzanine Card Interface 43 System Controller 50 I2C Bus...

Страница 4: ...Read Multiple Power Rails 75 Read Power Rails Continuously 76 FMC Tab 77 EEPROM Data Tab 79 Write Board EEPROM Data 80 Read Board EEPROM Data 81 Appendix F Additional Resources and Legal Notices 83 X...

Страница 5: ...tronic components when they are improperly handled and can result in total or intermittent failures Always follow ESD prevention procedures when removing and replacing components To prevent ESD damage...

Страница 6: ...mbedded USB to JTAG programming port JTAG programming header Programmable logic PL JTAG connector connected to HPIO bank 66 System Controller Zynq 7000 SoC XC7Z010 CLG225 One analog power module suppo...

Страница 7: ...INT 0 85V 12A VCCPAUX 1 8V 3A VCC_PSPLL 1 2V 3A VCCO_DDR 1 5V 6A VCCO_MIO 1 8V 6A VCCINT_AMS 0 85V 20A USB to UART Bridge Select I O Termination FMC2 Interface VCCO_HP HPC FMC3 Interface VCCO_HD LPC G...

Страница 8: ...on the back side of the board IMPORTANT The following figure is for reference only and might not reflect the current revision of the board Figure 2 Board Component Locations 26 29 30 31 31 31 31 31 3...

Страница 9: ...SW14 PS_POR_B Pushbutton and PS_SRST_B Pushbutton 16 J250 J251 VCCINT power probe SMA 17 J276 J277 VCCINT_AMS power probe SMA 18 J158 J159 J156 J194 PS GTR ref clock SMAs Serial Transceivers and Refe...

Страница 10: ...SW7 RFSoC PROGRAM Pushbutton 45 DS40 DS39 DS17 DS3 RFSoC DONE LED INIT LED STATUS LED and ERROR LED 46 J106 J216 VTT_HP external connector and selection header 47 J190 J189 J188 J187 J192 J191 J257 J...

Страница 11: ...otection use a power supply with a current limit set at 6A maximum CAUTION Do NOT apply 12V power to more than a single input source For example do not apply power to J73 and J27 at the same time CAUT...

Страница 12: ...MGTAVCC MGTAVTT MGTVCCAUX Maxim 15301 U28 0 85V at 12A max VCCPINT Maxim 15303 U48 1 8V at 3A max VCCPAUX Maxim 15303 U27 1 2V at 3A max VCC_PSPL L Maxim 15303 U11 1 5V at 6A max VCCO_DDR Maxim 15303...

Страница 13: ...hree phases at 20A phase VCCINT 0 85V Maxim MAX15303 U24 InTune digital point of load PoL controller 6A VCCAUX VCCAUX_IO 1 8V Maxim MAX15303 U47 InTune digital point of load PoL controller 6A VCCBRAM...

Страница 14: ...onitor with I2C interface MGTAVCC_GTR 0 85V INA226 U97 Current shunt and power monitor with I2C interface MGTAVTT_GTR 1 8V Utility Maxim MAX15301 U50 InTune digital point of load PoL controller 20A UT...

Страница 15: ...to the ENABLED position The following table lists the external power connectors for the different power rails Table 3 RFSoC Logic and Serial Transceiver Rails Power Rail Net Name External Supply Conne...

Страница 16: ...The pinouts for J4 and J145 are shown in the following figure J25 callout 39 Figure 2 Board Component Locations is used to connect to the analog power module PMBus The pinout for J25 is shown in the f...

Страница 17: ...FSoC RF data converters The analog power module connects to J131 J119 and J120 Two analog power modules are provided with the ZCU1285 board for evaluation One module is made by Intersil with part numb...

Страница 18: ...cterization kit Table 4 Analog Power Module Analog Rail Net Name Nominal Voltage V Maximum Current Rating A ADC_AVCC 0 925 2 00 ADC_AVCCAUX 1 8 2 00 DAC_AVCC 0 925 3 5 DAC_AVCCAUX 1 8 2 00 DAC_AVTT 2...

Страница 19: ...ion kit there is one GTY transceiver power module from Maxim Integrated provided for evaluation part number MAXREFDES87 The GTY transceiver power module is labeled GTY and connects to J174 and J155 Th...

Страница 20: ...U1285 board Table 5 Serial Transceiver Power Modules Serial Transceiver Rail Net Name Nominal Voltage V Maximum Current Rating A MGTAVCC 0 9 12 MGTAVTT 1 2 20 MGTVCCAUX 1 8 2 5 MGTAVCC_GTR 0 85 12 MGT...

Страница 21: ...lent embedded USB JTAG connector callout 8 Figure 2 Board Component Locations Xilinx Platform Cable USB II JTAG cable connector callout 9 Figure 2 Board Component Locations The ZCU1285 board comes wit...

Страница 22: ...DONE LED The DONE LED DS17 callout 45 Figure 2 Board Component Locations indicates the state of the DONE pin of the RFSoC When the DONE pin is High DS17 lights up indicating the RFSoC is successfully...

Страница 23: ...ction Headers Four 3 pin headers are provided for mode pin selection to set the boot mode for the RFSoC processor callout 12 Figure 2 Board Component Locations Install a jumper across pins 1 2 MIO_BUS...

Страница 24: ...llout 49 Figure 2 Board Component Locations provide access to global clock GC pins on the RFSoC The GC pins are connected to the SMA connectors as shown in the following table Table 8 Differential SMA...

Страница 25: ...onent Locations providing external access for these pins The I O pins can be connected to the onboard System Controller as additional GPIO between the two devices Note Install J7 to connect the user D...

Страница 26: ...W17 System Monitor The System Monitor SYSMON monitors the physical environment using on chip temperature and supply sensors up to 17 external analog inputs and an integrated analog to digital converte...

Страница 27: ...ale MPSoC only Digital GND Analog GND 470 nF 100 nF VCCPAUX 1 8V 3 VCCPAUX Supply Filter VREFP VREFN Package Pins X22896 051519 Quad SPI Flash Memory A single quad SPI device MT25QU01GBBB8ESF 0SIT 1 8...

Страница 28: ...Converters and Sampling Clocks The ZCU1285 board provides access to all of the RFSoC RF ADC and RF DAC signal and clock pins Each RF ADC and RF DAC is designed with 70 db isolation at 3 GHz The four...

Страница 29: ...2 VOUT_2 VOUT_1 VOUT_3 VOUT_0 CLK CLK C A Bulls Eye Connector Pad RF ADC Connector Pinout RF DAC Connector Pinout N P N P N P N P P P P N P N P P N N N N N P N P N P N P P P P N P N P P N N N N X22897...

Страница 30: ...5 J124 3307 012 AN2 ADC_VIN1_225_P 225 J124 3196 802 AN1 ADC_VIN1_225_N 225 J124 3194 401 AL5 ADC_VIN2_225_P 225 J124 3342 156 AL4 ADC_VIN2_225_N 225 J124 3339 779 AL2 ADC_VIN3_225_P 225 J124 3223 9 A...

Страница 31: ...llowing table Table 13 RF DAC Pins RFSoC U1 Net Name Tile Connector Trace Length mils Y5 DAC_VOUT0_228_P 228 J129 3366 712 Y4 DAC_VOUT0_228_N 228 J129 3364 991 Y2 DAC_VOUT1_228_P 228 J129 3209 197 Y1...

Страница 32: ...9 695 H5 DAC_VOUT0_231_P 231 J279 3265 511 H4 DAC_VOUT0_231_N 231 J279 3263 254 H2 DAC_VOUT1_231_P 231 J279 3111 166 H1 DAC_VOUT1_231_N 231 J279 3108 992 F5 DAC_VOUT2_231_P 231 J279 3243 78 F4 DAC_VOU...

Страница 33: ...CLK1 TX3 TX2 RX2 X22898 051519 PS GTR bank 505 has two additional reference clocks CLK2 and CLK3 which are brought out to two pairs of SMA connectors callout 18 Figure 2 Board Component Locations GTY...

Страница 34: ...29 J118 2580 324 P38 129_TX0_P 129 J118 2579 92 N37 129_TX1_N 129 J118 2828 966 N36 129_TX1_P 129 J118 2829 422 M39 129_TX2_N 129 J118 2684 658 M38 129_TX2_P 129 J118 2688 416 L37 129_TX3_N 129 J118 2...

Страница 35: ...1 684 C36 131_TX2_P 131 J281 3432 171 A37 131_TX3_N 131 J281 3180 526 A36 131_TX3_P 131 J281 3181 286 GTY Transceiver Reference Clock Inputs Information for each GTY transceiver clock input is shown i...

Страница 36: ...P 505 J39 4302 524 AE42 PS_RX3_N 505 J39 3174 371 AE41 PS_RX3_P 505 J39 3173 868 AH36 PS_TX0_N 505 J39 3400 509 AH35 PS_TX0_P 505 J39 3399 45 AG38 PS_TX1_N 505 J39 3468 187 AG37 PS_TX1_P 505 J39 3467...

Страница 37: ...m Controller see Appendix E System Controller To connect to the SuperClock 2 Module using the I2C bus see I2C Bus Management Table 18 SuperClock 2 Interface Connections RFSoC U1 Schematic Net Name J36...

Страница 38: ...ntial pair RF clocks for RF DACs The SuperClock RF2 module schematic BOM and Allegro board files are in the XTP document package on the Zynq UltraScale RFSoC ZCU1285 Characterization Kit website The S...

Страница 39: ...s 5 J11 External reference clock input 6 J10 Single ended reference clock output 7 DS1 DS2 DS3 DS5 PLL lock indicator LEDs PLL A PLL A has four differential output SMA pairs that are used as RF sampli...

Страница 40: ...equency for this clock is 12 8 MHz Programming the Clocks The clocks on the SuperClock RF2 Module can be programmed using the System Controller user interface SCUI See Appendix E System Controller A s...

Страница 41: ...is for a clock channel The balun board details are listed in the following table The balun board schematic BOM and Allegro board files are in the XTP document package on the Zynq UltraScale RFSoC ZCU...

Страница 42: ...aren BD3150N50100AHF 4000 6000 MHz HF_CH1 Anaren BD3150N50100AHF 4000 6000 MHz CLK Anaren BD60120N50100AHF 3500 12000 MHz HF_CH2 Anaren BD3150N50100AHF 4000 6000 MHz HF_CH3 Anaren BD3150N50100AHF 4000...

Страница 43: ...pairs FMC3 LPC connector JA4 provides connectivity for 34 differential user defined pairs 34 LA pairs 4 differential clocks IMPORTANT The VADJ voltage on the FMC2 LPC connector tracks VCCO_HP and on t...

Страница 44: ...FMC2_HA10P K13 AN18 FMC2_HA10N K14 AN19 FMC2_HA11P J12 AP19 FMC2_HA11N J13 AP21 FMC2_HA12P F13 AR21 FMC2_HA12N F14 AT20 FMC2_HA13P E12 AT19 FMC2_HA13N E13 AU21 FMC2_HA14P J15 AU20 FMC2_HA14N J16 AT18...

Страница 45: ...B05P E24 AN15 FMC2_HB05N E25 AU17 FMC2_HB06P K28 AU16 FMC2_HB06N K29 AN16 FMC2_HB07P J27 AP16 FMC2_HB07N J28 AN13 FMC2_HB08P F28 AP13 FMC2_HB08N F29 AR16 FMC2_HB09P E27 AR15 FMC2_HB09N E28 AR14 FMC2_H...

Страница 46: ...A30 FMC2_LA02N H8 B32 FMC2_LA03P G9 A32 FMC2_LA03N G10 B28 FMC2_LA04P H10 A28 FMC2_LA04N H11 B30 FMC2_LA05P D11 B31 FMC2_LA05N D12 B27 FMC2_LA06P C10 A27 FMC2_LA06N C11 C30 FMC2_LA07P H13 C31 FMC2_LA0...

Страница 47: ...2_LA22P G24 B25 FMC2_LA22N G25 D24 FMC2_LA23P D23 C24 FMC2_LA23N D24 C26 FMC2_LA24P H28 B26 FMC2_LA24N H29 D23 FMC2_LA25P G27 C23 FMC2_LA25N G28 E26 FMC2_LA26P D26 D26 FMC2_LA26N D27 E22 FMC2_LA27P C2...

Страница 48: ...7 AU10 FMC3_LA01_CCP D8 AV10 FMC3_LA01_CCN D9 AP11 FMC3_LA02P H7 AP10 FMC3_LA02N H8 AP12 FMC3_LA03P G9 AR11 FMC3_LA03N G10 AR10 FMC3_LA04P H10 AT10 FMC3_LA04N H11 AR12 FMC3_LA05P D11 AT12 FMC3_LA05N D...

Страница 49: ...MC3_LA20N G22 H13 FMC3_LA21P H25 G13 FMC3_LA21N H26 J14 FMC3_LA22P G24 J13 FMC3_LA22N G25 K15 FMC3_LA23P D23 K14 FMC3_LA23N D24 L14 FMC3_LA24P H28 K15 FMC3_LA24N H29 M17 FMC3_LA25P G27 L17 FMC3_LA25N...

Страница 50: ...signal When SYS_POR is reasserted the System Controller is reconfigured from the design stored on its dedicated quad SPI QSPI flash memory System Controller Status LEDs DS1 DS12 DS16 and DS27 callout...

Страница 51: ...U46 U53 U55 and U58 in the following figure J121 and J125 callout 13 Figure 2 Board Component Locations are used to enable or disable the bus repeaters and isolate the System Controller or the RFSoC...

Страница 52: ...free virtual COM port VCP drivers for the host computer These drivers permit the CP2108 to appear as four COM ports to communications application software for example Tera Term or Hyper Terminal that...

Страница 53: ...to UART Connection RFSoC U1 Schematic Net Name Device U32 Pin Function Direction IOSTANDA RD Pin Function Direction C33 MIO35 TX OUTPUT MIO35_UART_TX 15 RX INPUT D31 MIO34 RX INPUT MIO34_UART_RX 16 T...

Страница 54: ...27 Fan Power Connections Fan Wire Header Pin Black J99 1 FAN_NEG Red J99 2 VCC12_SW Blue J99 3 NC The following figure shows the heat sink fan power connector J99 Chapter 1 ZCU1285 Board Features and...

Страница 55: ...Figure 21 Heat Sink Fan Power Connector J99 Chapter 1 ZCU1285 Board Features and Operation UG1348 v1 0 July 16 2019 www xilinx com ZCU1285 Board User Guide 55 Send Feedback...

Страница 56: ...on IEC CE Electromagnetic Compatibility EN 55022 2010 Information Technology Equipment Radio Disturbance Characteristics Limits and Methods of Measurement EN 55024 2010 Information Technology Equipmen...

Страница 57: ...EE Compliance Schemes in some countries to help manage customer returns at end of life If you have purchased Xilinx branded electrical or electronic products in the EU and are intending to discard the...

Страница 58: ...left ENABLED SW2 10 VCCO_DDR Upper left ENABLED SW2 11 VCCO_MIO Upper left ENABLED SW2 12 VCCINT_AMS Upper left ENABLED J87 GTY PMBUS CTRL Upper left GND 2 3 J215 PMBUS CTRL Center Left GND 2 3 J40 PO...

Страница 59: ...ion Jumper DIP Switch Position Comments J12 CLK_DIFF_1_N Lower Middle Installed J13 CLK_DIFF_2_P Lower Middle Installed J14 CLK_DIFF_2_N Lower Middle Installed Appendix B Default Jumper Settings UG134...

Страница 60: ...GND HA12_N GND LA09_P LA10_P GND DP4_M2C_P 15 GND HA14_P GND LA12_P GND HA16_P LA09_N LA10_N GND DP4_M2C_N 16 HA17_P_CC HA14_N LA11_P LA12_N HA15_P HA16_N GND GND DP6_M2C_P GND 17 HA17_N_CC GND LA11_N...

Страница 61: ...DP4_C2M_N 36 GND HB18_P GND LA33_P GND HB21_P 3P3V GND DP6_C2M_P GND 37 HB17_P_CC HB18_N LA32_P LA33_N HB20_P HB21_N GND 12P0V DP6_C2M_N GND 38 HB17_N_CC GND LA32_N GND HB20_N GND 3P3V GND GND DP5_C2M...

Страница 62: ...on the ZCU1285 board schematic Identify the appropriate pins and replace the following net names with net names in the user RTL See the Vivado Design Suite User Guide Using Constraints UG903 for more...

Страница 63: ...Zynq 7000 SoC using the Interface 1 port of the Silicon Labs USB to Quad UART described in the USB to Quad UART Bridge See the following figure Figure 22 Silicon Labs Interface 1 COM Port Connecting...

Страница 64: ...dow of the SCUI is displayed see the following figure On the left side of the window is the system controller controls and on the right side is a log of the operations Figure 24 SCUI Main Window Appen...

Страница 65: ...lowing figure is used to set the frequency of the SuperClock 2 Module clock sources see SuperClock 2 Module and the SuperClock RF2 Module clock sources see SuperClock RF2 Module Figure 25 Clocks Tab U...

Страница 66: ...equency Auto Select and Set Si5368 Frequency Free Running The free running option uses the onboard XA XB crystal as the active clock routed to the Si5368 internal PLL The auto select option uses one o...

Страница 67: ...up Enter the desired boot frequencies in the Set Boot Frequency tab and press Enter to save the boot frequency to EEPROM see the following figure After the boot frequencies are set the Logging pane sh...

Страница 68: ...M see the following figure Figure 30 CLK 101 Restore Device Defaults Tab View Last Set CLK 101 Frequencies The last frequencies that were written to the CLK 101 Module can be viewed using the Last Set...

Страница 69: ...Note Do not move or rename any of the folders because the SCUI relies on the directory structure to find the clock files Figure 33 CLK 103 Clock Files Note For each of the following operations severa...

Страница 70: ...MX2592 PLL A B and C Frequency Enter the full file name of the clock file with the desired frequency for PLL A in the field next to the Type file name in the clockFiles lmx2592a folder and press Enter...

Страница 71: ...e desired boot frequencies in each file name field In addition LMK04208 output divisors and enable disable settings can also be entered and stored After clock files and values are entered click the re...

Страница 72: ...iew Last Set CLK 103 Frequencies The last frequencies that were written to the CLK 103 Module can be viewed using the Last Set tab Click the relevant last set button to view the last frequency written...

Страница 73: ...s to the default values see the following figure Figure 38 CLK 103 Reset Device For New Input Tab Power Tab The SCUI can read the onboard INA226 power rail measurements for each of the power rails lis...

Страница 74: ...TT MGTVCCAUX PS GTR transceiver MGTRAVCC MGTRAVTT Read a Single Power Rail To read a single power rail measurement click the corresponding button with the power rail name on it The power voltage and c...

Страница 75: ...ls To read multiple power rail measurements at once check the box to the left of each power rail button and click Run All see the following figure Appendix E System Controller UG1348 v1 0 July 16 2019...

Страница 76: ...tions at the bottom of the SCUI Select either the Run Continuously or Run x times then click the power rail button to read the measurements To stop the reading click Terminate Running Operations see t...

Страница 77: ...m Controller and the programmable clock resources on each card Table 31 FMC Card Clock Sources Xilinx FMC Card Description Clock Source 1 Clock Source 2 XM101 LVDS QSE card Si570 SI570 XM104 Serial tr...

Страница 78: ...bank voltage is connected to VADJ on the FMC interface to allow the FMC card to track the bank voltage that is connected to it The system controller can change the bank voltage that is connected to ea...

Страница 79: ...ck to 200 MHz on an XM104 card connected to JA3 EEPROM Data Tab The ZCU1285 System Controller includes an EEPROM that is used to store board information The information entered into the Board Informat...

Страница 80: ...Data Write Board EEPROM Data To write EEPROM data use the Set buttons highlighted in the following figure Appendix E System Controller UG1348 v1 0 July 16 2019 www xilinx com ZCU1285 Board User Guide...

Страница 81: ...OM Data Read Board EEPROM Data To read EEPROM data use the Get buttons highlighted in the following figure Appendix E System Controller UG1348 v1 0 July 16 2019 www xilinx com ZCU1285 Board User Guide...

Страница 82: ...ta button opens a window displaying the full contents of the EEPROM memory see the following figure Figure 48 Get EEPROM Data Window Appendix E System Controller UG1348 v1 0 July 16 2019 www xilinx co...

Страница 83: ...lp Documentation and Tutorials On Windows select Start All Programs Xilinx Design Tools DocNav At the Linux command prompt enter docnav Xilinx Design Hubs provide links to documentation organized by d...

Страница 84: ...9 Samtec Inc Bulls Eye interace Please Read Important Legal Notices The information disclosed to you hereunder the Materials is provided solely for the selection and use of Xilinx products To the max...

Страница 85: ...ER AUTOMOTIVE PRODUCTS IDENTIFIED AS XA IN THE PART NUMBER ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE SAFETY APPLICATION UNLESS...

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