Xilinx XC4000E Series, Руководство пользователя

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XC4000E and XC4000X Series Field Programmable Gate Arrays
4-18 March 30, 1998 (Version 1.5)
Fast Carry Logic
Each CLB F and G function generator contains dedicated
arithmetic logic for the fast generation of carry and borrow
signals. This extra output is passed on to the function gen-
erator in the adjacent CLB. The carry chain is independent
of normal routing resources.
Dedicated fast carry logic greatly increases the efficiency
and performance of adders, subtractors, accumulators,
comparators and counters. It also opens the door to many
new applications involving arithmetic operation, where the
previous generations of FPGAs were not fast enough or too
inefficient. High-speed address offset calculations in micro-
processor or graphics systems, and high-speed addition in
digital signal processing are two typical applications.
The two 4-input function generators can be configured as a
2-bit adder with built-in hidden carry that can be expanded
to any length. This dedicated carry circuitry is so fast and
efficient that conventional speed-up methods like carry
generate/propagate are meaningless even at the 16-bit
level, and of marginal benefit at the 32-bit level.
This fast carry logic is one of the more significant features
of the XC4000 Series, speeding up arithmetic and counting
into the 70 MHz range.
The carry chain in XC4000E devices can run either up or
down. At the top and bottom of the columns where there
are no CLBs above or below, the carry is propagated to the
right. (See
Figure 12 .) In order to improve speed in the
high-capacity XC4000X devices, which can potentially
have very long carry chains, the carry chain travels upward
only, as shown in
Figure 13 . Additionally, standard inter-
connect can be used to route a carry signal in the down-
ward direction.
Figure 14 on page 4-20 shows an XC4000E CLB with ded-
icated fast carry logic. The carry logic in the XC4000X is
similar, except that COUT exits at the top only, and the sig-
nal CINDOWN does not exist. As shown in
Figure 14 , the
carry logic shares operand and control inputs with the func-
tion generators. The carry outputs connect to the function
generators, where they are combined with the operands to
form the sums.
Figure 15 on page 4-21 shows the details of the carry logic
for the XC4000E. This diagram shows the contents of the
box labeled “CARRY LOGIC” in
Figure 14 . The XC4000X
carry logic is very similar, but a multiplexer on the pass-
through carry chain has been eliminated to reduce delay.
Additionally, in the XC4000X the multiplexer on the G4 path
has a memory-programmable 0 input, which permits G4 to
Enable
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
X6749
4
READ ADDRESS
MUX
Enable
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
4
READ ADDRESS
MUX
G'
4 G1 • • • G4
F1 • • • F4
C1 • • • C4
4
F'
WE
D1/A4 D0
EC
4
H'
Figure 11: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)