Chapter 1
Transceiver and Tool Overview
Introduction to the UltraScale
Architecture
The Xilinx
®
UltraScale™ architecture is the first ASIC-class architecture to enable multi-hundred
gigabit-per-second levels of system performance with smart processing, while efficiently routing
and processing data on-chip. UltraScale architecture-based devices address a vast spectrum of
high-bandwidth, high-utilization system requirements by using industry-leading technical
innovations, including next-generation routing, ASIC-like clocking, 3D-on-3D ICs, multiprocessor
SoC (MPSoC) technologies, and new power reduction features. The devices share many building
blocks, providing scalability across process nodes and product families to leverage system-level
investment across platforms.
Virtex
®
Ult™ devices provide the highest performance and integration capabilities in a
FinFET node, including both the highest serial I/O and signal processing bandwidth, as well as
the highest on-chip memory density. As the industry's most capable FPGA family, the Virtex
Ult devices are ideal for applications including 1+ Tb/s networking and data center and
fully integrated radar/early-warning systems.
Virtex
®
UltraScale™ devices provide the greatest performance and integration at 20 nm,
including serial I/O bandwidth and logic capacity. As the industry's only high-end FPGA at the
20 nm process node, this family is ideal for applications including 400G networking, large scale
ASIC prototyping, and emulation.
Kintex
®
Ult™ devices provide the best price/performance/watt balance in a FinFET
node, delivering the most cost-effective solution for high-end capabilities, including transceiver
and memory interface line rates as well as 100G connectivity cores. Our newest mid-range family
is ideal for both packet processing and DSP-intensive functions and is well suited for applications
including wireless MIMO technology, Nx100G networking, and data center.
UG581 (v1.0) January 4, 2019
Virtex Ult GTM Transceivers
5