March 2002 Release
749
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Alphabetical Instruction Listing
R
tlbia
TLB Invalidate All
Description
This is a privileged instruction.
All TLB entries are invalidated. The instruction invalidates a TLB entry by clearing the
valid (V) bit in the TLBHI portion of the entry. No other field within the TLB entry is
modified by this instruction.
The TLB is invalidated regardless of whether address translation is enabled. A context-
synchronizing instruction should follow the
tlbia
instruction to guarantee that the effect of
invalidating the TLB is visible to subsequent instructions.
Registers Altered
•
None.
Exceptions
•
Program—Attempted execution of this instruction from user mode.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
•
Reserved bits containing a non-zero value.
Compatibility
This instruction is defined as optional by the operating-environment architecture level
(OEA) of the PowerPC architecture and the PowerPC embedded-environment
architecture. Because it is optional it is not implemented by all PowerPC processors.
tlbia
X Instruction Form
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
370
0
0
6
2
1
3
1
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