Xilinx Virtex-II Pro PPC405, Руководство пользователя

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732 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 11: Instruction Set
R
stswx
Store String Word Indexed
Description
An effective address (EA) is calculated by adding an index to a base address, which are
formed as follows:
• The contents of register r B are used as the index.
• If the r A field is 0, the base address is 0.
• If the r A field is not 0, the contents of register r A are used as the base address.
Let n specify the byte count contained in XER[TBC].
Let nr specify the number of registers to load with data. nr
=
CEIL( n
÷
4).
GPRs r S through r S
+
nr
−
1 are stored into n consecutive bytes starting at the memory
address referenced by EA. The sequence of registers wraps around to r 0 if necessary. The
bytes within each register are stored beginning with the most-significant byte and ending
with the least-significant byte, until the byte count is satisfied.
If XER[TBC]
=
0, stswx is treated as a no-operation.
Pseudocode
EA
←
( r A|0) + ( r B)
n
←
XER[TBC]
r
←
r S
−
1
i
←
0
do while n > 0
if i
=
0
then r
←
r + 1
if r
=
32
then r
←
0
MS(EA, 1)
←
(GPR(r)
i:i+7
)
i
←
i + 8
if i
=
32
then i
←
0
EA
←
EA + 1
n
←
n
−
1
Registers Altered
• None.
stswx r S , r A, r B
X Instruction Form
31 r S r A r B 661 0
0 6 1
1 1
6 2
1 3
1