Xilinx Virtex-II Pro PPC405, Руководство пользователя

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350 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 2: Operational Concepts
R
Big-Endian Mapping
The big-endian mapping of structure s follows. The contents of each byte, as defined in
structure s , is shown as a (hexadecimal) number or character (for the string elements). Data
addresses (in hexadecimal) are shown below the corresponding data value.
Little-Endian Mapping
The little-endian mapping of structure s follows.
Little-Endian Byte Ordering Support
Except as noted, this book describes the processor from the perspective of big-endian
operations. However, the PPC405 processor also fully supports little-endian operations.
This support is provided by the endian (E) storage attribute described in the following
sections. The endian-storage attribute is defined by both the PowerPC embedded-
environment architecture and PowerPC Book-E architecture.
Little-endian mode , defined by the PowerPC architecture, is not implemented by the PPC405.
Little-endian mode does not support true little-endian memory accesses. This is because
little-endian mode modifies memory addresses rather than reordering bytes as they are
accessed. Memory-address modification restricts how the processor can access misaligned
data and I/O. The PPC405 little-endian support does not have these restrictions.
11 12 13 14
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
21 22 23 24 25 26 27 28
0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
31 32 33 34 ’A’ ’B’ ’C’ ’D’
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
’E’ ’F’ ’G’ 51 52
0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F
61 62 63 64
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
14 13 12 11
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
28 27 26 25 24 23 22 21
0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
34 33 32 31 ’A’ ’B’ ’C’ ’D’
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
’E’ ’F’ ’G’ 52 51
0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F
64 63 62 61
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27