338
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 1:
Introduction to the PPC405
R
Programmable Interval Timer
The
programmable interval timer
(PIT) is a 32-bit register that is decremented at the time-base
increment frequency. The PIT register is loaded with a delay value. When the PIT count
reaches 0, a PIT interrupt occurs. Optionally, the PIT can be programmed to automatically
reload the last delay value and begin decrementing again.
Fixed Interval Timer
The
fixed interval timer
(FIT) causes an interrupt when a selected bit in the time-base register
changes from 0 to 1. Programmers can select one of four predefined bits in the time-base
for triggering a FIT interrupt.
Watchdog Timer
The
watchdog timer
causes a hardware reset when a selected bit in the time-base register
changes from 0 to 1. Programmers can select one of four predefined bits in the time-base
for triggering a reset, and the type of reset can be defined by the programmer.
Note:
The time-base register alone does not cause interrupts to occur.
Debug
The PPC405 debug resources include special debug modes that support the various types
of debugging used during hardware and software development. These are:
•
Internal-debug mode
for use by ROM monitors and software debuggers
•
External-debug mode for use by JTAG debuggers
•
Debug-wait mode
, which allows the servicing of interrupts while the processor appears
to be stopped
•
Real-time trace mode
, which supports event triggering for real-time tracing
Debug events are
supported
that allow developers to manage the debug process. Debug
modes and debug events are controlled using debug registers in the processor. The debug
registers are accessed either through software running on the processor or through the
JTAG port. The JTAG port can also be used for board tests.
The debug modes, events, controls, and interfaces provide a powerful combination of
debug resources for hardware and software development tools.
,
describes these resources in detail.
PPC405 Interfaces
The PPC405 provides a set of interfaces that supports the attachment of cores and user
logic. The software resources used to manage the PPC405 interfaces are described in the
. For information on the hardware operation, use,
and electrical characteristics of these interfaces, refer to the
. The following interfaces are provided:
•
Processor local bus interface
•
Device control register interface
•
Clock and power management interface
•
JTAG port interface
•
On-chip interrupt controller interface
•
On-chip memory controller interface
Processor Local Bus
The
processor local bus (PLB) interface
provides a 32-bit address and three 64-bit data buses
attached to the instruction-cache and data-cache units. Two of the 64-bit buses are attached
to the data-cache unit, one supporting read operations and the other supporting write
operations. The third 64-bit bus is attached to the instruction-cache unit to support
instruction fetching.
Содержание Virtex-II Pro PPC405
Страница 1: ...R Volume 2 a PPC405 User Manual Virtex II Pro Platform FPGA Developer s Kit March 2002 Release...
Страница 14: ...322 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Preface R...
Страница 252: ...560 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...
Страница 260: ...568 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...
Страница 562: ...870 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...
