Xilinx Virtex-II Pro PPC405, Руководство пользователя

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520 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 7: Exceptions and Interrupts
R
Instruction TLB-Miss Interrupt (0x1200)
Interrupt Classification
• Noncritical—return using the rfi instruction.
• Synchronous.
• Precise.
Description
Instruction TLB-miss exceptions can occur only when instruction translation is enabled
(MSR[IR]
=
1). An instruction TLB-miss exception occurs when no valid TLB entry is found
with both:
• A TAG field that matches the instruction effective-address page number (EA[EPN]).
• A TID field that matches the current process ID (PID).
Instruction TLB-miss exceptions are associated with the fetching of an instruction from
memory. However, an instruction TLB-miss interrupt occurs only if an attempt is made to
execute the instruction as required by the sequential-execution model. Speculative fetches
that are later discarded do not cause instruction TLB-miss interrupts.
Software cannot disable instruction TLB-miss interrupts.
See TLB Access , page 479 , for more information on how TLB hits and misses are
determined.
Affected Registers
Register Value After Interrupt
SRR0 Loaded with the effective address of the instruction that caused the instruction
TLB-miss exception.
SRR1 Loaded with a copy of the MSR at the point the interrupt occurs.
SRR2 Not used.
SRR3
ESR
DEAR
MSR [AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR]
←
0.
[CE, ME, DE]
←
Unchanged.