March 2002 Release
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Virtex-II Pro™ Platform FPGA Documentation
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Chapter 7
Exceptions and Interrupts
The PowerPC embedded-environment architecture extends the base PowerPC exception
and interrupt mechanism in the following ways:
•
A dual-level interrupt structure is defined supporting critical and noncritical
interrupts.
•
New save/restore registers are defined in support of the dual-level interrupt
structure.
•
A new interrupt-return instruction is defined in support of the dual-level interrupt
structure.
•
New special-purpose registers are defined for recording exception information.
•
New exceptions and interrupts are defined.
This chapter describes the exceptions recognized by the PPC405D5 and how the interrupt
mechanism responds to those exceptions.
Overview
Exceptions
are events detected by the processor that often require action by system
software. Most exceptions are unexpected and are the result of error conditions. A few
exceptions can be programmed to occur through the use of exception-causing instructions.
Some exceptions are generated by external devices and communicated to the processor
using external signalling. Still other exceptions can occur when pre-programmed
conditions are recognized by the processor.
Interrupts
are automatic control transfers that occur as a result of an exception. An
interrupt occurs when the processor suspends execution of a program after detecting an
exception. The processor saves the suspended-program machine state and a return address
into the suspended program. This information is stored in a pair of special registers, called
save/restore registers
. A predefined machine state is loaded by the processor, which transfers
control to an
interrupt handler
. An interrupt handler is a system-software routine that
responds to the interrupt, often by correcting the condition causing the exception. System
software places interrupt handlers at predefined addresses in physical memory and the
interrupt mechanism automatically transfers control to the appropriate handler based on
the exception condition.
An interrupt places the processor in both privileged mode and real mode (instruction-
address and data-address relocation are disabled). Interrupts are context-synchronizing
events. All instructions preceding the interrupted instruction are guaranteed to have
completed execution when the interrupt occurs. All instructions following the interrupted
instruction (in the program flow) are discarded.
Returning from an interrupt handler to an interrupted program requires that the old
machine state and program return address be restored from the save/restore register pair.
This is accomplished using a
return-from-interrupt
instruction. Like interrupts, return-from-
interrupt instructions are context synchronizing.
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