Xilinx Virtex-II Pro PPC405, Руководство пользователя

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Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
PowerPC Architecture Overview
R
privileged software from the PowerPC architecture to the PPC405 is in many cases
straightforward because of the simplifications made by the PowerPC embedded-
environment architecture. Software developers who are concerned with cross-
compatibility of privileged software between the PPC405 and other PowerPC
implementations should refer to
Appendix E, PowerPC
®
6xx/7xx Compatibility .
Latitude Within the PowerPC Architecture Levels
Although the PowerPC architecture defines parameters necessary to ensure compatibility
among PowerPC processors, it also allows a wide range of options for individual
implementations. These are:
• Some resources are optional, such as certain registers, bits within registers,
instructions, and exceptions.
• Implementations can define additional privileged special-purpose registers (SPRs),
exceptions, and instructions to meet special system requirements, such as power
management in processors designed for very low-power operation.
• Implementations can define many operating parameters. For example, the PowerPC
architecture can define the possible condition causing an alignment exception. A
particular implementation can choose to solve the alignment problem without
causing an exception.
• Processors can implement any architectural resource or instruction with assistance
from software (that is, they can trap and emulate) as long as the results (aside from
performance) are identical to those specified by the architecture. In this case, a
complete implementation requires both hardware and software.
• Some parameters are defined at one level of the architecture and defined more
specifically at another. For example, the UISA defines conditions that can cause an
alignment exception and the OEA specifies the exception itself.
Features Not Defined by the PowerPC Architecture
Because flexibility is an important feature of the PowerPC architecture, many aspects of
processor design (typically relating to the hardware implementation) are not defined,
including the following:
System-Bus Interface
Although many implementations can share similar interfaces, the PowerPC architecture
does not define individual signals or the bus protocol. For example, the OEA allows each
implementation to specify the signal or signals that trigger a machine-check exception.
Cache Design
The PowerPC architecture does not define the size, structure, replacement algorithm, or
mechanism used for maintaining cache coherency. The PowerPC architecture supports,
but does not require, the use of separate instruction and data caches.
Execution Units
The PowerPC architecture is a RISC architecture, and as such has been designed to
facilitate the design of processors that use pipelining and parallel execution units to
maximize instruction throughput. However, the PowerPC architecture does not define the
internal hardware details of an implementation. For example, one processor might
implement two units dedicated to executing integer-arithmetic instructions and another
might implement a single unit for executing all integer instructions.
Other Internal Microarchitecture Issues
The PowerPC architecture does not specify the execution unit responsible for executing a
particular instruction. The architecture does not define details regarding the instruction-
fetch mechanism, how instructions are decoded and dispatched, and how results are
written to registers. Dispatch and write-back can occur in-order or out-of-order. Although