Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 417
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Multiply-Accumulate Instruction-Set Extensions
R
Negative Multiply-Accumulate Low-Halfword to Word Instructions
Table 3-45 shows the PPC405 negative multiply-accumulate low-halfword to word instructions.
These instructions multiply the low halfword of both source operands, r A[16:31] and
r B[16:31], producing a signed 32-bit product. This product is negated and added to the
value in the destination register, r D, producing a 33-bit intermediate result (this is the same
as subtracting the product from r D). Generally, r D is loaded with the lower-32 bits of the
33-bit intermediate result. However, if the instruction performs saturating arithmetic and
the intermediate result overflows,
r D is loaded with the nearest representable value (see
Modulo and Saturating Arithmetic , page 405 ).
For each type of instruction shown in Table 3-45 , the “Operation” column indicates the
negative multiply-accumulate operation performed. The column also shows, on an
instruction-by-instruction basis, how the XER and CR registers are updated (if at all).
Figure 3-32: Negative Multiply-Accumulate High-Halfword to Word Operation
UG011_24_033101
r D
0 31
0 32
r A
0 31 16
r B
0 31 15
×
r D
0 31
+
Intermediate Result
−
1
1