Xilinx Virtex-4 FX FPGA, Руководство пользователя, Страница: 11 / 30

ML42 x User Guide www.xilinx.com 11
UG087 (v1.3) May 30, 2008
Introduction
R
Figure 1 shows a block diagram of the board.
Figure 1: Virtex-4 FPGA ML42 x Platform Block Diagram
XGI XGI
LED s
GP S W s
PB S W 3
PB S W 4
O S C
S MA
O S C
S ocket
S MA
2 X 1
S MA
2 X1
Right Angle S MA
Right Angle S MA
Right Angle S MA
Right Angle S MA
PROGRAM
MGT MGT
S y s tem ACE
UART
DONE
LED
INIT
LED
LED s
GP S W s
PB S W 1
PB S W 2
Power Bu s and S witche s
5V J a ck 5V Brick -or-
MGT_VTT_RX_LEFT J a ck
MGT_VTT_RX_RIGHT J a ck
MGT_VTT_TX_LEFT J a ck
MGT_VTT_TX_RIGHT J a ck
AVCCAUX_TX J a ck
AVCCAUX_RX J a ck
AVCCAUXMGT J a ck
MGT_VREF J a ck
1.5V - 2.5V
1.5V - 2.5V
2.5V
1.2V
LV
D
S
*
UG0 8 7_01_092006
Virtex-4
FPGA
(DUT)
MGT
Launch S MA
Active High Active High
DIFF
S MA
DIFF
S MA CC*
O S C
S MA
O S C
S ocket
S MA
2 X 1
S MA
2 X1
MGT MGT
LVD S *
MGT Clock
MGT Clock
DIFF
S MA
1.2V
1.2V
VCCO J a ck
VCCINT J a ck
VAUX J a ck
VCCINT
VAUX
VCCO
V5
1.5V
1.5V
12 Tr a n s ceiver s = 4 8 S MA s in FF672
16 Tr a n s ceiver s = 64 S MA s in FF1152
20 Tr a n s ceiver s = 8 0 S MA s in FF1517
* Note: LVD S he a der s a nd clock c a p ab le region a l clock s
a re not a v a il ab le on ML421 pl a tform s .
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