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RocketIO™ Transceiver User Guide

57

UG024 (v3.0) February 22, 2007

Reset/Power Down

R

Data Path Latency

With the many configurations of the MGT, the both transmit and receive data path
latencies vary. Below are several tables that provide approximate latencies for common
configurations.

Reset/Power Down

The receiver and transmitter have their own synchronous reset inputs. The transmitter
reset recenters the transmission FIFO, and resets all transmitter registers and the 8B/10B
encoder. The receiver reset recenters the receiver elastic buffer, and resets all receiver
registers and the 8B/10B decoder. Neither reset signal has any effect on the PLLs.

After the DCM-locked signal is asserted, the resets can be asserted. The resets must be
asserted for two USRCLK2 cycles to ensure correct initialization of the FIFOs. Although
both the transmit and receive resets can be attached to the same signal, separate signals are
preferred. This allows the elastic buffer to be cleared in case of an over/underflow without
affecting the ongoing TX transmission. The following example is an implementation that
resets all three data-width transceivers.

Table 2-6:

Latency through Various Transmitter Components/Processes

Component/Process

Latency

TX Fabric/GT Interface

1 Byte Data Path:

2.5 TXUSRCLK2 cycles
1.25 TXUSRCLK cycles

2 Byte Data Path:

1 TXUSRCLK2 cycle
1 TXUSRCLK cycle

4 Byte Data Path:

1.25 TXUSRCLK2 cycles
2.5 TXUSRCLK cycles

TX CRC

included

7 TXUSRCLK cycles

bypassed

1 TXUSRCLK cycle

8B/10B Encoder

included

1 TXUSRCLK cycle

bypassed

1 TXUSRCLK cycle

TX FIFO

4 TXUSRCLK cycles (

±

0.5)

TX SERDES

SERDES_10B = FALSE:
1.5 TXUSRCLK cycles

SERDES_10B = TRUE:
0.5 TXUSRCLK cycles (approx.)

Table 2-7:

Latency through Various Receiver Components/Processes

Component/Process

Latency

RX SERDES

1.5 recovered clock (RXRECCLK) cycles

Comma Detect/Realignment

2.5 or 3.5 recovered clock cycles
(some bits bypass one register, depending on comma alignment)

8B/10B Decoder

included

1 recovered clock cycle

bypassed

1 recovered clock cycle

RX FIFO

18 RXUSRCLK cycles (

±

0.5)

RX GT/Fabric Interface

1 Byte Data Path:

2.5 RXUSRCLK2 cycles
1.25 RXUSRCLK cycles

2 Byte Data Path:

1 RXUSRCLK2 cycle
1 RXUSRCLK cycle

4 Byte Data Path:

1.25 RXUSRCLK2 cycles
2.5 RXUSRCLK cycles

Product Not Recommended for New Designs

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Содержание RocketIO

Страница 1: ...R RocketIO Transceiver User Guide UG024 v3 0 February 22 2007 Product Not Recommended for New Designs...

Страница 2: ...uitry entirely embodied in its products Xilinx provides any design code or information shown or described herein as is By providing the design code or information as one possible implementation of a f...

Страница 3: ...1 5 Corrected pinouts for FF1152 package device column 2VP20 30 LOC Constraints rows GT_X0_Y0 and GT_X0_Y1 Corrected section CRC Latency and Table 2 20 to express latency in terms of TXUSRCLK and RXUS...

Страница 4: ...FER_USE in Chapter 2 Corrected erroneous USRCLK2 to RXUSRCLK RXUSRCLK2 Table 2 20 Added footnotes qualifying the maximum receive side latency parameters given in the table Section FIBRE_CHAN in Chapte...

Страница 5: ...nd Package combinations table Figure 3 9 page 113 Added new Figure 3 10 page 110 showing Example Power Filtering PCB Layout for Four MGTs in Device with Internal Capacitors Bottom Layer Modified the t...

Страница 6: ...e 119 Corrected I O standard name to LVDS_25_DT Powering the RocketIO Transceivers page 120 Added section Pin Connections on the Unused RocketIO Transceivers The POWERDOWN Port page 120 Added that tog...

Страница 7: ...of Available Ports 24 Primitive Attributes 29 Modifiable Primitives 34 Byte Mapping 38 Chapter 2 Digital Design Considerations Clocking 39 Clock Signals 39 BREFCLK 41 Clock Ratio 42 Digital Clock Mana...

Страница 8: ...passing of 8B 10B Encoding 66 SERDES Alignment 67 Overview 67 Serializer 67 Deserializer 67 Ports and Attributes 67 ALIGN_COMMA_MSB 67 ENPCOMMAALIGN ENMCOMMAALIGN 68 PCOMMA_DETECT MCOMMA_DETECT 70 COM...

Страница 9: ...HBONDDONE 83 CHBONDI CHBONDO 83 RXCLKCORCNT RXLOSSOFSYNC 83 Troubleshooting 83 CRC Cyclic Redundancy Check 84 Overview 84 CRC Operation 84 CRC Generation 84 CRC Latency 85 Ports and Attributes 85 TX_C...

Страница 10: ...9 Power Conditioning 109 Voltage Regulator Selection and Use 109 Termination Voltage 110 Passive Filtering 111 High Speed Serial Trace Design 115 Routing Serial Traces 115 Differential Trace Design 11...

Страница 11: ...es 147 XAPP669 PPC405 PPE Reference System Using Virtex II Pro RocketIO Transceivers 147 XAPP670 Minimizing Receiver Elastic Buffer Delay in the Virtex II Pro RocketIO Transceiver 148 XAPP680 HD SDI T...

Страница 12: ...12 www xilinx com RocketIO Transceiver User Guide UG024 v3 0 February 22 2007 R Product Not Recommended for New Designs...

Страница 13: ...ap with 8B 10B Bypassed 65 Figure 2 14 10 Bit RX Data Map with 8B 10B Bypassed 65 Figure 2 15 8B 10B Parallel to Serial Conversion 66 Figure 2 16 4 Byte Serial Structure 66 Figure 2 17 Synchronizing C...

Страница 14: ...xternal Capacitors Bottom Layer 115 Figure 3 12 Single Ended Trace Geometry 116 Figure 3 13 Microstrip Edge Coupled Differential Pair 117 Figure 3 14 Stripline Edge Coupled Differential Pair 117 Figur...

Страница 15: ...DATA_WIDTHs 43 Table 2 6 Latency through Various Transmitter Components Processes 57 Table 2 7 Latency through Various Receiver Components Processes 57 Table 2 8 Reset and Power Control Descriptions...

Страница 16: ...onments 118 Chapter 4 Simulation and Implementation Table 4 1 LOC Grid Package Pins Correlation for FG256 456 FF672 123 Table 4 2 LOC Grid Package Pins Correlation for FG676 FF896 and FF1152 124 Table...

Страница 17: ...allowing compatibility with other serial system voltage levels Four levels of programmable pre emphasis AC and DC coupling Programmable 50 75 on chip termination eliminating the need for external term...

Страница 18: ...support xilinx com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Description URL Tutori...

Страница 19: ...depending on the protocol used so that the serial data is correctly decoded into parallel data Typographical The following typographical conventions are used in this document Convention Meaning or Us...

Страница 20: ...itive material that has been omitted allow block block_name loc1 loc2 locn Convention Meaning or Use Example Convention Meaning or Use Example Blue text Cross reference link to a location in the curre...

Страница 21: ..._10B attribute see Table 1 3 Table 1 1 Number of RocketIO Cores per Device Type Device RocketIO Cores Device RocketIO Cores XC2VP2 4 XC2VP40 0 or 12 XC2VP4 4 XC2VP50 0 or 16 XC2VP7 8 XC2VP70 16 or 20...

Страница 22: ...tput Polarity RXN GNDA TXN DS083 2_04_090402 POWERDOWN RXRECCLK RXPOLARITY RXREALIGN RXCOMMADET RXRESET RXCLKCORCNT RXLOSSOFSYNC RXDATA 15 0 RXDATA 31 16 RXCHECKINGCRC RXCRCERR RXNOTINTABLE 3 0 RXDISP...

Страница 23: ...ding the clock frequency for USRCLK and USRCLK2 discussed in Digital Clock Manager DCM Examples in Chapter 2 The data and control ports for GT_CUSTOM must also reflect this change in data width by con...

Страница 24: ...trol that is used only by slaves which is driven by a transceiver s CHBONDO port CHBONDO 2 O 4 Channel bonding control that passes channel bonding and clock correction control to other transceivers CO...

Страница 25: ...es that the received data is a K character when asserted High Included in Byte mapping If 8B 10B decoding is bypassed it remains as the first bit received Bit a of the 10 bit encoded data see Figure 2...

Страница 26: ...r comma detect channel bonding clock correction logic and other internal receive registers It does not reset the receiver PLL RXRUNDISP 3 O 1 2 4 Signals the running disparity 0 negative 1 positive in...

Страница 27: ...RC value by XORing with the bits specified in attribute TX_CRC_FORCE_VALUE This input can be used to test detection of CRC errors at the receiver TXINHIBIT I 1 If a logic High the TX differential pair...

Страница 28: ...s on the width of TXDATA Notes 1 The GT_CUSTOM ports are always the maximum port size 2 GT_FIBRE_CHAN and GT_ETHERNET ports do not have the three CHBOND or ENCHANSYNC ports 3 The port size changes wit...

Страница 29: ...f protocols like Gigabit Ethernet are oriented in byte pairs with commas always in even first byte formation this can be set to TRUE Otherwise it should be set to FALSE 2 For 32 bit data path primitiv...

Страница 30: ...is High and RXRESET is Low TRUE Master transceiver initiates channel bonding only the first time it is possible channel bonding sequence is detected in input following negated RXRESET and asserted ENC...

Страница 31: ...equently clock correction can occur CLK_COR_SEQ_ _ 11 bit vectors that define the sequence for clock correction The attribute used depends on the CLK_COR_SEQ_LEN and CLK_COR_SEQ_2_USE CLK_COR_SEQ_2_US...

Страница 32: ...ONLY TRUE FALSE controls the raising of RXCHARISCOMMA on an invalid comma FALSE Raise RXCHARISCOMMA on 0011111xxx if DEC_PCOMMA_DETECT is TRUE and or on 1100000xxx if DEC_MCOMMA_DETECT is TRUE regardl...

Страница 33: ...l bit rate TRUE 1 10 Refer to XAPP572 when considering running in this serial range FALSE 1 20 FALSE supports a serial bitstream range of 1 0 Gb s to 3 125 Gb s TRUE supports a range of 600 Mb s to 1...

Страница 34: ...OFF 2 OFF OFF CHAN_BOND_OFFSET 8 8 0 CHAN_BOND_ONE_SHOT FALSE 2 FALSE TRUE CHAN_BOND_SEQ_1_1 00101111100 00000000000 00000000000 CHAN_BOND_SEQ_1_2 00000000000 00000000000 00000000000 CHAN_BOND_SEQ_1_3...

Страница 35: ...ALID_COMMA_ONLY TRUE TRUE TRUE MCOMMA_10B_VALUE 1100000101 1100000000 1100000000 MCOMMA_DETECT TRUE TRUE TRUE PCOMMA_10B_VALUE 0011111010 0011111000 0011111000 PCOMMA_DETECT TRUE TRUE TRUE REF_CLK_V_S...

Страница 36: ...T Table 1 8 Default Attribute Values GT_FIBRE_CHAN GT_INFINIBAND and GT_XAUI Attribute Default GT_FIBRE_CHAN Default GT_INFINIBAND Default GT_XAUI ALIGN_COMMA_MSB FALSE FALSE FALSE CHAN_BOND_LIMIT 1 1...

Страница 37: ...LK_COR_SEQ_LEN 4 1 1 CLK_CORRECT_USE TRUE TRUE TRUE COMMA_10B_MASK 1111111000 1111111000 1111111000 CRC_END_OF_PKT Note 3 Note 3 K29_7 1 CRC_FORMAT FIBRE_CHAN INFINIBAND USER_MODE 1 CRC_START_OF_PKT N...

Страница 38: ...X_DECODE_USE TRUE TRUE TRUE RX_LOS_INVALID_INCR 1 1 1 1 1 1 RX_LOS_THRESHOLD 4 1 4 1 4 1 RX_LOSS_OF_SYNC_FSM TRUE 1 TRUE 1 TRUE 1 SERDES_10B FALSE 1 FALSE 1 FALSE 1 TERMINATION_IMP 50 1 50 1 50 1 TX_B...

Страница 39: ...ference clock becomes available to ensure the PMA is properly initialized The reference clock also clocks a Digital Clock Manager DCM or a BUFG to generate all of the other clocks for the MGT Never ru...

Страница 40: ...K 1 Input Clock from FPGA used for writing the TX Buffer This clock must be frequency locked to REFCLK for proper operation RXUSRCLK2 Input Clock from FPGA used to clock RX data and status between the...

Страница 41: ...same clock inputs for all packages An attribute REF_CLK_V_SEL and a port REFCLKSEL determine which reference clock is used for the MGT PMA block Figure 2 1 shows how REFCLK and BREFCLK are selected th...

Страница 42: ...input reference clock for the DCM The other clocks are generated by the DCM The DCM establishes a desired phase relationship between TXUSRCLK TXUSRCLK2 etc in the FPGA core and REFCLK at the pad NOTE...

Страница 43: ...SERDES_10B TX_DATA_WIDTH RX_DATA_WIDTH REFCLK TXUSRCLK RXUSRCLK TXUSRCLK2 RXUSRCLK2 FALSE 1 CLKIN CLK0 CLK2X180 FALSE 2 CLKIN CLK0 CLK0 FALSE 4 CLKIN CLK180 1 CLKDV divide by 2 TRUE 1 CLKIN CLKDV div...

Страница 44: ...O out std_logic end component component DCM port CLKIN in std_logic CLKFB in std_logic DSSEN in std_logic PSINCDEC in std_logic PSEN in std_logic PSCLK in std_logic RST in std_logic CLK0 out std_logic...

Страница 45: ...FCLK U2_BUFG BUFG port map I CLK0_W O USRCLK_M end TWO_BYTE_CLK_arch Verilog Template Module TWO_BYTE_CLK Description Verilog Submodule DCM for 2 byte GT Device Virtex II Pro Family module TWO_BYTE_CL...

Страница 46: ...shown in Figure 2 3 Example 2 Four Byte Clock If a 4 byte or 1 byte data path is chosen the ratio between USRCLK and USRCLK2 changes The time it take for the SERDES to serialize the parallel data requ...

Страница 47: ...e UNISIM VCOMPONENTS ALL pragma translate_on entity FOUR_BYTE_CLK is port REFCLKIN in std_logic RST in std_logic USRCLK_M out std_logic USRCLK2_M out std_logic REFCLK out std_logic LOCK out std_logic...

Страница 48: ...CLK2X out std_logic CLK2X180 out std_logic CLKDV out std_logic CLKFX out std_logic CLKFX180 out std_logic LOCKED out std_logic PSDONE out std_logic STATUS out std_logic_vector 7 downto 0 end component...

Страница 49: ...Submodule DCM for 4 byte GT Device Virtex II Pro Family module FOUR_BYTE_CLK REFCLKIN REFCLK USRCLK_M USRCLK2_M DCM_LOCKED input REFCLKIN output REFCLK output USRCLK_M output USRCLK2_M output DCM_LOCK...

Страница 50: ...ng scheme example USRCLK2_M is twice as fast as USRCLK_M It is also phase shifted 180 for falling edge alignment VHDL Template Module ONE_BYTE_CLK Description VHDL submodule DCM for 1 byte GT Device V...

Страница 51: ...onent BUFG port I in std_logic O out std_logic end component component IBUFG port I in std_logic O out std_logic end component component DCM port CLKIN in std_logic CLKFB in std_logic DSSEN in std_log...

Страница 52: ...tiation U_DCM DCM port map CLKIN REFCLK CLKFB USRCLK_M DSSEN GND PSINCDEC GND PSEN GND PSCLK GND RST RST CLK0 CLK0_W CLK2X180 CLK2X180_W LOCKED LOCK BUFG Instantiation U_BUFG IBUFG port map I REFCLKIN...

Страница 53: ...LK_M wire USRCLK2_M wire DCM_LOCKED wire REFCLKINBUF wire clk_i wire clk_2x_180 DCM dcm1 CLKFB USRCLK_M CLKIN REFCLKINBUF DSSEN 1 b0 PSCLK 1 b0 PSEN 1 b0 PSINCDEC 1 b0 RST 1 b0 CLK0 clk_i CLK90 CLK180...

Страница 54: ...CLK UG024_29_013103 CLKDV CLKDV divide by 2 MGT clock input invert ers acceptable skew GT_std_1 REFCLKSEL REFCLK TXUSRCLK RXUSRCLK TXUSRCLK2 RXUSRCLK2 CLKIN CLKFB RST DCM CLK0 0 BUFG BUFG REFCLK_P IBU...

Страница 55: ...plexed Clocking Scheme without DCM As with Example 1b Two Byte Clock without DCM the DCMs shown in Figure 2 9 may be removed if TXDATA and RXDATA are not clocked off the FPGA See Figure 2 10 However t...

Страница 56: ...m this bit clock through a divide by 20 process When the data input is kept static however the recovered clock does not frequency lock to the reference clock exactly but can deviate from it by up to 4...

Страница 57: ...TX transmission The following example is an implementation that resets all three data width transceivers Table 2 6 Latency through Various Transmitter Components Processes Component Process Latency T...

Страница 58: ...Description RXRESET Synchronous receive system reset recenters the receiver elastic buffer and resets the 8B 10B decoder comma detect channel bonding clock correction logic and other receiver registe...

Страница 59: ...0010 then RST 0 end if end if end process end RTL Verilog Template Module gt_reset Description Verilog Submodule reset for4 byte GT Device Virtex II Pro Family module gt_reset USRCLK2_M DCM_LOCKED RST...

Страница 60: ...s used for Gigabit Ethernet Fibre Channel and InfiniBand The decoder separately detects both disparity errors and out of band errors A disparity error occurs when a 10 bit character is received that e...

Страница 61: ...r is enabled and should coincide with TXBYPASS8B10B being set Low In this mode the received data output from the RXDATA port is decoded data either 8 16 or 32 bits wide However when the attribute is s...

Страница 62: ...B encoding is enabled not bypassed 1 2 or 4 bits mapped to number of bytes of data path width 1 8B 10B encoding bypassed disabled 1 2 or 4 bits mapped to number of bytes of data path width Function 8B...

Страница 63: ...is bypassed this port is undefined TXRUNDISP TXRUNDISP is a status port that is byte mapped to TXDATA This port indicates the running disparity after the byte of TXDATA is encoded When High the dispar...

Страница 64: ...s usually indicates data corruption bit errors or transmission of an invalid control character It can also occur in cases where normal disparity is not required such as in the Vitesse Disparity Exampl...

Страница 65: ...HARDISPMODE bits become bits b and a respectively of the 10 bit encoded data that the transceiver must transmit to the receiving terminal Figure 2 13 illustrates the TX data map during 8B 10B bypass D...

Страница 66: ...TXDATA 23 16 TXDATA 15 8 and finally TXDATA 7 0 The 2 byte path transmits TXDATA 15 8 and then TXDATA 7 0 HDL Code Examples Transceiver Bypassing of 8B 10B Encoding 8B 10B encoding can be bypassed by...

Страница 67: ...nously aligned If a comma is detected and the data is aligned no further alignment alteration takes place If a comma is received and realignment is necessary the data is realigned and RXREALIGN is ass...

Страница 68: ...this problem ENPCOMMAALIGN and ENMCOMMAALIGN should be passed through a flip flop that is clocked with RXRECCLK These flip flops should be located near the MGT and RXRECCLK should use local interconne...

Страница 69: ...nment R Figure 2 18 and Figure 2 19 show floorplanner layouts for the two examples given above Figure 2 18 Top MGT Comma Control Flip Flop Ideal Locations Figure 2 19 Bottom MGT Comma Control Flip Flo...

Страница 70: ...UE is 0011111000 the comma detection unit will recognize the following characters as plus commas 0011111000 K28 7 0011111001 K28 1 0011111010 K28 5 0011111011 through 0011111111 not valid comma charac...

Страница 71: ...k data recovery circuit This circuit uses a fully monolithic Phase Locked Loop PLL which does not require any external components The clock data recovery circuit extracts both phase and frequency from...

Страница 72: ...he FPGA core reads data via the read pointer under control of RXUSRCLK The half full half empty condition of the buffer gives a cushion for the differing clock rates This operation continues indefinit...

Страница 73: ...g how many IDLEs are received and whether CLK_COR_KEEP_IDLE is TRUE or FALSE For example if three IDLEs are received and CLK_COR_KEEP_IDLE is set to TRUE at least one IDLE sequence must remain after c...

Страница 74: ...e Channel 4 byte The attributes CLK_COR_SEQ_ _ and CLK_COR_SEQ_LEN below define the CCS that the PCS recognizes Both SEQ_1 and SEQ_2 can be used at the same time if multiple CCSs are required As shown...

Страница 75: ...if needed to recenter the elastic buffer When set to TRUE it forces the clock correction logic to retain at least one clock correction sequence per continuous stream of clock correction sequences Exa...

Страница 76: ...a is valid or not and if the MGT is synchronized on the data For applications using the 8B 10B encoding scheme the RX_LOSS_OF_SYNC FSM does this It can be programmed to lose sync after a specified num...

Страница 77: ..._LOSS_OF_SYNC_FSM a TRUE FALSE attribute indicates what the output of the RXLOSSOFSYNC port see below means Note RX_LOSS_OF_SYNC_FSM only indicates valid data It is assumed that the PLL is locked The...

Страница 78: ...he FSM moves to state RESYNC Otherwise the FSM remains in state SYNC_ACQUIRED RESYNC RXLOSSOFSYNC 01 The FSM waits in this state for four RXRECCLK cycles and then goes to state SYNC_ACQUIRED unless an...

Страница 79: ...ine corresponding points in the several channels In the bottom half of Figure 2 22 the shaded P bytes represent these special characters Each receiver recognizes the P channel bonding character and re...

Страница 80: ...set the transceiver attribute to off The possible values that can be used are shown in Table 2 18 Note All standards that use both clock correction and channel bonding require a gap greater than or e...

Страница 81: ...CHANSYNC many applications will require that the channels be aligned only once CHAN_BOND_ONE_SHOT TRUE allows the Master to initiate a channel bonding only once This remains true even if more channel...

Страница 82: ...ines the maximum number of bytes by which the Slave can lag the Master Due to internal pipelining the equation should be CHAN_BOND_WAIT 3 5 bytes of bytes Slave may lag Master For example if CHAN_BOND...

Страница 83: ...om going out of sync if for instance one Slave repeated a CCS while another skipped RXCLKCORCNT RXLOSSOFSYNC These signals are mainly used for clock correction However they can convey some information...

Страница 84: ...below for Gigabit Ethernet Fibre Channel Infiniband and user defined modes The CRC recognizes the SOP Start of Packet EOP End of Packet and other packet features to identify the beginning and end of d...

Страница 85: ...rolled by RX_CRC_USE and TX_CRC_USE Whenever these attributes are set to TRUE CRC is used The four modes are defined in the subsections following USER_MODE USER_MODE is the simplest CRC methodology Th...

Страница 86: ...at begin with K28 5 D21 5 or K28 5 D10 5 When the RocketIO CRC determines that the running disparity must be inverted to satisfy Fibre Channel requirements it will convert the second byte of the EOP f...

Страница 87: ...ata path K28 5 must be strobed into the MGT on rising TXUSRCLK2 only when TXUSRCLK is High Note Minimum data length for this mode is defined by the protocol requirements Note For correct operation of...

Страница 88: ...s must be one of the defined K characters see Table B 2 page 143 These must be different than a clock correction sequence CCS or IDLE sequence otherwise the CRC will mistake the CCS or IDLE for SOP EO...

Страница 89: ...tter and Elastic Receiver Buffers Both the transmitter and the receiver include buffers FIFOs in the data path This section gives the reasons for including the buffers and outlines their operation Tra...

Страница 90: ...TRUE since channel bonding and clock correction use the receive buffer for realignment When the buffer is bypassed the user logic must be clocked with RXRECCLK Miscellaneous Signals Ports and Attribu...

Страница 91: ...ables internal serial loopback TX_DIFF_CTRL PRE_EMPHASIS These two attributes control analog functionality of the MGT The TX_DIFF_CTRL attribute is used to compensate for signal attenuation in the lin...

Страница 92: ...ng normal operation LOOPBACK should be set to 00 01 Internal Parallel Mode Internal Parallel Mode allows testing the transmit and receive interface logic PCS without having to go into the PMA section...

Страница 93: ...Logic must be designed in the FPGA fabric to handle comma alignment for the 32 bit primitives when implementing certain protocols Note that FPGA logic is not required for 1 byte and 2 byte configurat...

Страница 94: ...synchronized with RXDATA It is not possible to adjust RXCLKCORCNT appropriately for shifted delayed RXDATA because RXCLKCORCNT is summary data and the summary for the shifted case cannot be recalcula...

Страница 95: ...IBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION INCLUDING BUT NOT LIMITED TO...

Страница 96: ...1 reg 15 0 rxdata_reg reg 1 0 rxisk_reg reg 3 0 aligned_rxisk reg byte_sync reg 3 0 wait_to_sync reg count This process maintains wait_to_sync and count which are used only to maintain output sync thi...

Страница 97: ...after initialization of the elastic buffer always posedge usrclk2 begin if rxreset rxrealign sync 1 b0 else if wait_to_sync 4 b0000 rxchariscomma3 rxchariscomma1 sync 1 b1 end This process generates...

Страница 98: ...FOR YOUR IMPLEMENTATION XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS I...

Страница 99: ...chariscomma3 IN std_logic rxchariscomma1 IN std_logic END ENTITY align_comma_32 ARCHITECTURE translated OF align_comma_32 IS SIGNAL rxdata_reg std_logic_vector 15 DOWNTO 0 SIGNAL rxisk_reg std_logic_v...

Страница 100: ...gned_data 31 24 Output aligned_data is considered to be in sync when a comma is seen on rxdata as indicated by rxchariscomma3 or 1 after the counter wait_to_sync has reached 0 indicating that commas s...

Страница 101: ...0 rxdata 15 DOWNTO 0 rxisk_reg 1 DOWNTO 0 rxisk 1 DOWNTO 0 IF rxchariscomma3 1 THEN rxdata_hold 31 DOWNTO 0 rxdata 31 DOWNTO 0 rxisk_hold 3 DOWNTO 0 rxisk 3 DOWNTO 0 byte_sync 0 ELSE IF rxchariscomma...

Страница 102: ...102 www xilinx com RocketIO Transceiver User Guide UG024 v3 0 February 22 2007 Chapter 2 Digital Design Considerations R Product Not Recommended for New Designs...

Страница 103: ...ts of transistors configured as shown in Figure 3 1 CML uses a positive supply and offers easy interface requirements In this configuration both legs of the driver VP and VN sink current with one leg...

Страница 104: ...be driven down lossy line media and increases the signal to noise ratio at the receiver It should be noted that high pre emphasis settings are not appropriate for short links a fraction of the maximum...

Страница 105: ...024 v3 0 February 22 2007 Pre emphasis Techniques R Figure 3 2 Alternating K28 5 with No Pre Emphasis Figure 3 3 K28 5 with Pre Emphasis UG024_17_020802 UG024_18_020802 Logic High Strong High Strong L...

Страница 106: ...bruary 22 2007 Chapter 3 Analog Design Considerations R Figure 3 4 Eye Diagram 10 Pre Emphasis 20 FR4 Worst Case Conditions Figure 3 5 Eye Diagram 33 Pre Emphasis 20 FR4 Worst Case Conditions ug024_36...

Страница 107: ...ignificant instants of a signal from their ideal positions in time ITU Jitter is typically expressed in a decimal fraction of Unit Interval UI e g 0 3 UI Total Jitter Deterministic Jitter DJ Random Ji...

Страница 108: ...A sufficient number of transitions must be present in the data stream for CDR to work properly The CDR circuit is guaranteed to work with 8B 10B encoding Further CDR requires approximately 5 000 tran...

Страница 109: ...DS083 To operate properly the RocketIO transceiver requires a certain level of noise isolation from surrounding noise sources For this reason it is required that both dedicated voltage regulators and...

Страница 110: ...capacitors In cases where more than 16 MGTs are powered from a single regulator an additional 1 0 F capacitor is required for every two additional MGTs Tantalum is the recommended capacitor type for...

Страница 111: ...t does not contain capacitors External Each transceiver power pin requires one capacitor and one ferrite bead The capacitors must be of value 0 22 F in an 0603 EIA SMT package of X7R or X5R dielectric...

Страница 112: ...ase in a package with internal capacitors in another case in a package with external capacitors The device in Figure 3 9 is in an FF672 package which has eight transceivers total four on the top edge...

Страница 113: ...the package so it is necessary to have both capacitors and ferrite beads mounted on the PCB Figure 3 10 shows the top PCB layer with lands for the capacitors and ferrite beads of the VTTX and VTRX sup...

Страница 114: ...ceiver User Guide UG024 v3 0 February 22 2007 Chapter 3 Analog Design Considerations R Figure 3 10 Example Power Filtering PCB Layout for Four MGTs In Device with External Capacitors Top Layer Product...

Страница 115: ...ing the differential traces to within 50 mils 1 27 mm produces a robust design Since signals propagate in FR4 PCB traces at approximately 180 ps per inch a difference of 50 mils produces a timing skew...

Страница 116: ...ndividual trace must be slightly higher than half of the target differential impedance A field solver should be used to determine the exact trace geometry suited to the specific application Figure 3 1...

Страница 117: ...where RocketIO transceivers are interfaced with other RocketIO transceivers or other Mindspeed transceivers that have compatible differential and common mode voltage specifications Passive components...

Страница 118: ...d with 2 5V are DC coupled the common mode voltage will establish itself at around 1 7V to 1 8V The VTRX and VTTX voltages for different coupling environments are summarized in Table 3 8 Figure 3 16 D...

Страница 119: ...in Figure 3 18 Pletronics LV1145B LVDS Outputs See the Pletronics website for detailed information The circuit shown in Figure 3 19 must be used to interface the oscillator s LVDS outputs to the LVDS...

Страница 120: ...RX pins can be unconnected If the MGT is used as a receiver the TX pins can be left unconnected If the design uses the transmitter the RX pins can safely be left unconnected and oscillations will not...

Страница 121: ...www xilinx com xlnx xil_sw_updates_home jsp Select HSPICE and Eldo Models and then Virtex II Pro from the pull down menus Online registration is required Follow the instructions on the web page to re...

Страница 122: ...on UG024_08_020802 CHBONDI CHBONDO SLAVE_1_HOP CHBONDO CHBONDI SLAVE_2_HOPS CHBONDI CHBONDO SLAVE_1_HOP CHBONDO CHBONDI SLAVE_2_HOPS CHBONDI CHBONDO SLAVE_1_HOP CHBONDO CHBONDI SLAVE_2_HOPS CHBONDI CH...

Страница 123: ...NPAD respectively The power pins are adjacent to these pins in the package pin diagrams of the User Guide Table 4 1 LOC Grid Package Pins Correlation for FG256 456 FF672 LOC Constraints FG256 FG456 FF...

Страница 124: ...A20 A19 A18 A29 A28 A27 A26 A29 A28 A27 A26 GT_X2_Y0 AF18 AF17 AF16 AF15 AF12 AF11 AF10 AF9 AK14 AK13 AK12 AK11 AK14 AK13 AK12 AK11 AP17 AP16 AP15 AP14 AP21 AP20 AP19 AP18 AP25 AP24 AP23 AP22 GT_X2_Y1...

Страница 125: ...8 AW17 AW16 AW24 AW23 AW22 AW21 AW28 AW27 AW26 AW25 BB29 BB28 BB27 BB26 GT_X3_Y1 A19 A18 A17 A16 A24 A23 A22 A21 A28 A27 A26 A25 A29 A28 A27 A26 GT_X4_Y0 AW11 AW10 AW9 AW8 AW19 AW18 AW17 AW16 AW24 AW2...

Страница 126: ...126 www xilinx com RocketIO Transceiver User Guide UG024 v3 0 February 22 2007 Chapter 4 Simulation and Implementation R Product Not Recommended for New Designs...

Страница 127: ...e of these clocks RXUSRCLK RXUSRCLK2 and TXUSRCLK2 have I Os that are synchronous to them The following table gives a brief description of all of these clocks For an in depth discussion of clocking th...

Страница 128: ...RXPOLARITY RXREALIGN RXCOMMADET RXRESET RXCLKCORCNT RXLOSSOFSYNC RXDATA 15 0 RXDATA 31 16 RXCHECKINGCRC RXCRCERR RXNOTINTABLE 3 0 RXDISPERR 3 0 RXCHARISK 3 0 RXCHARISCOMMA 3 0 RXRUNDISP 3 0 RXBUFSTATU...

Страница 129: ...Hold time after clock edge where x C Control inputs D Data inputs Setup Hold Time Examples TGCCK_RRST TGCKC_RRST Setup hold times of RX Reset input relative to rising edge of RXUSRCLK2 TGDCK_TDAT TGC...

Страница 130: ...in Table A 1 along with the RocketIO signals that are synchronous to each clock No signals are synchronous to REFCLK or TXUSRCLK A timing diagram Figure A 2 illustrates the timing relationships Table...

Страница 131: ...tputs RXCLKCORCNT 2 0 TGCKST_RBSTA Status outputs RXBUFSTATUS 1 0 TGCKST_RCCRC Status output RXCHECKINGCRC TGCKST_RCRCE Status output RXCRCERR TGCKST_CHBD Status output CHBONDDONE TGCKST_RKCH Status o...

Страница 132: ...tputs CONFIGOUT Clock TTX2PWH Clock pulse width High state TXUSRCLK2 TTX2PWH Clock pulse width Low state TXUSRCLK2 Table A 4 Parameters Relative to the TX User Clock2 TXUSRCLK2 Continued Parameter Fun...

Страница 133: ...7 Timing Parameter Tables and Diagram R Figure A 2 RocketIO Transceiver Timing Relative to Clock Edge CLOCK CONTROL INPUTS CONTROL OUTPUTS DATA OUTPUTS DATA INPUTS TxGWH TGCCK TxGWL TGCKC TGCKCO TGCKD...

Страница 134: ...134 www xilinx com RocketIO Transceiver User Guide UG024 v3 0 February 22 2007 Appendix A RocketIO Transceiver Timing Model R Product Not Recommended for New Designs...

Страница 135: ...j D0 0 000 00000 100111 0100 011000 1011 D1 0 000 00001 011101 0100 100010 1011 D2 0 000 00010 101101 0100 010010 1011 D3 0 000 00011 110001 1011 110001 0100 D4 0 000 00100 110101 0100 001010 1011 D5...

Страница 136: ...00111 1001 011000 1001 D1 1 001 00001 011101 1001 100010 1001 D2 1 001 00010 101101 1001 010010 1001 D3 1 001 00011 110001 1001 110001 1001 D4 1 001 00100 110101 1001 001010 1001 D5 1 001 00101 101001...

Страница 137: ...1001 010100 1001 D0 2 010 00000 100111 0101 011000 0101 D1 2 010 00001 011101 0101 100010 0101 D2 2 010 00010 101101 0101 010010 0101 D3 2 010 00011 110001 0101 110001 0101 D4 2 010 00100 110101 0101...

Страница 138: ...011110 0101 100001 0101 D31 2 010 11111 101011 0101 010100 0101 D0 3 011 00000 100111 0011 011000 1100 D1 3 011 00001 011101 0011 100010 1100 D2 3 011 00010 101101 0011 010010 1100 D3 3 011 00011 1100...

Страница 139: ...0011 100001 1100 D31 3 011 11111 101011 0011 010100 1100 D0 4 100 00000 100111 0010 011000 1101 D1 4 100 00001 011101 0010 100010 1101 D2 4 100 00010 101101 0010 010010 1101 D3 4 100 00011 110001 110...

Страница 140: ...101011 0010 010100 1101 D0 5 101 00000 100111 1010 011000 1010 D1 5 101 00001 011101 1010 100010 1010 D2 5 101 00010 101101 1010 010010 1010 D3 5 101 00011 110001 1010 110001 1010 D4 5 101 00100 11010...

Страница 141: ...0110 011000 0110 D1 6 110 00001 011101 0110 100010 0110 D2 6 110 00010 101101 0110 010010 0110 D3 6 110 00011 110001 0110 110001 0110 D4 6 110 00100 110101 0110 001010 0110 D5 6 110 00101 101001 0110...

Страница 142: ...1101 0001 100010 1110 D2 7 111 00010 101101 0001 010010 1110 D3 7 111 00011 110001 1110 110001 0001 D4 7 111 00100 110101 0001 001010 1110 D5 7 111 00101 101001 1110 101001 0001 D6 7 111 00110 011001...

Страница 143: ...ble B 1 Valid Data Characters Continued Data Byte Name Bits HGF EDCBA Current RD abcdei fghj Current RD abcdei fghj Table B 2 Valid Control Characters K Characters Special Code Name Bits HGF EDCBA Cur...

Страница 144: ...144 www xilinx com RocketIO Transceiver User Guide UG024 v3 0 February 22 2007 Appendix B 8B 10B Valid Characters R Product Not Recommended for New Designs...

Страница 145: ...a and to output 10 bits of extracted data to the user interface This module can be used with the Virtex II Pro RocketIO Multi Gigabit Transceiver MGT to achieve line rates of 200 Mb s to 1000 Mb s Whe...

Страница 146: ...implies a need for clock recovery at the receiver which in turn requires a guaranteed minimum number of transitions in the incoming serial data stream The mechanism to achieve this transition density...

Страница 147: ...ICAP The solution uses a Virtex II Pro device with an IBM PowerPC 405 PPC405 processor to perform a partial reconfiguration of the RocketIO multi gigabit transceivers MGTs pre emphasis and differentia...

Страница 148: ...a format It also presents several implementation examples and reference designs for an HD SDI transmitter implemented using the Virtex II Pro FPGA XAPP681 HD SDI Receiver Using Virtex II Pro RocketIO...

Страница 149: ...d with the programmable logic of the Virtex II Pro devices makes it possible to implement multi rate SDI interfaces XAPP687 64B 66B Encoder Decoder This application note describes the encoding and dec...

Страница 150: ...Attachment Unit Interface PCI Express Serial RapidIO Fibre Channel Gigabit Ethernet Aurora Xilinx proprietary link layer protocol This document presents characterization data taken on Virtex II Pro d...

Страница 151: ...alternative design solutions using the Virtex II Pro Platform FPGA with RocketIO transceivers The four external devices discussed here are the Vitesse single channel VSC7123 the Vitesse quadchannelVS...

Страница 152: ...152 www xilinx com RocketIO Transceiver User Guide UG024 v3 0 February 22 2007 Appendix C Related Online Documents R Product Not Recommended for New Designs...

Страница 153: ...IFF_CTRL 91 Attributes table 29 B BREFCLK and REF_CLK_V_SEL 32 41 and REFCLKSEL 25 41 and serial speed 39 pin numbers 41 when how to use 41 Buffers Fabric Interface 89 ports and attributes 90 transmit...

Страница 154: ...upply passive filtering 111 power conditioning 109 Power Supply Circuit Using Approved Regulator figure 110 Pre emphasis available values 104 overview 104 scope screen captures 105 106 Q Qualified Lin...

Страница 155: ...g Parameters 129 Total Jitter DJ RJ 107 Transmitter and Elastic Receiver Buffers 89 Transmitter Buffer FIFO 89 U User Guide conventions online references 20 port and attribute names 19 typographical 1...

Страница 156: ...156 www xilinx com RocketIO Transceiver User Guide UG024 v3 0 February 22 2007 R Product Not Recommended for New Designs...

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