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ML628 Board User Guide

UG771 (v1.0.1) June 28, 2011

Preface:

About This Guide

Online Document

The following conventions are used in this document:

Convention

Meaning or Use

Example

Courier font

Messages, prompts, and 
program files that the system 
displays

speed grade: - 100

Courier bold

Literal commands that you enter 
in a syntactical statement

ngdbuild

 

design_name

Helvetica bold

Commands that you select from 
a menu 

File 

→

 

 Open

Keyboard shortcuts

Ctrl+C

Italic font

Variables in a syntax statement 
for which you must supply 
values

ngdbuild

 

design_name

References to other manuals

See the 

Command Line Tools User 

Guide 

for more information.

Emphasis in text

If a wire is drawn so that it 
overlaps the pin of a symbol, the 
two nets are 

not 

connected.

Convention

Meaning or Use

Example

Blue text

Cross-reference link to a location 
in the current document

See the section 

“Additional 

Resources”

 for details.

Refer to 

“Title Formats” in 

Chapter 1

 for details.

Blue, underlined text

Hyperlink to a website (URL)

Go to 

http://www.xilinx.com

 

for the latest speed files.

Содержание ML628

Страница 1: ...ss mainly focus on the distribution of electronic components Line cards we deal with include Microchip ALPS ROHM Xilinx Pulse ON Everlight and Freescale Main products comprise IC Modules Potentiometer...

Страница 2: ...ML628 Virtex 6 FPGA GTX and GTH Transceiver Characterization Board User Guide UG771 v1 0 1 July 6 2011...

Страница 3: ...h technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTI...

Страница 4: ...onnector 15 FPGA Configuration 17 PROG_B Push Button 18 DONE LED 18 INIT LED 19 System ACE Controller 19 System ACE Controller Reset 19 Configuration Address DIP Switches 19 JTAG Isolation Jumpers 19...

Страница 5: ...ww xilinx com ML628 Board User Guide UG771 v1 0 1 June 28 2011 Appendix A Default Jumper Positions Appendix B VITA 57 1 FMC HPC Connector Pinout Appendix C ML628 Master UCF Listing Appendix D Referenc...

Страница 6: ...and GTH transceiver characterization board Appendix A Default Jumper Positions lists the jumpers that must be installed on the board for proper operation Appendix B VITA 57 1 FMC HPC Connector Pinout...

Страница 7: ...ile Open Keyboard shortcuts Ctrl C Italic font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the Command Line Tools User Guide f...

Страница 8: ...supply jacks for optional use of external power supplies JTAG configuration port for use with Platform Cable USB or Parallel Cable III IV cables System ACE controller Separate power modules supportin...

Страница 9: ...irtex 6 FPGA XC6VHX380T 2FFG1923C 12V Power In FMC Interface FMC1 FMC2 ANSI VITA 57 1 2008 v1 1 System ACE Controller System Monitor Interface I2C Bus Management GTX Transceiver Power Module FPGA Powe...

Страница 10: ...k inputs J167 J170 1e Regulation inhibit J289 13 SuperClock 2 module 1f External power supply jacks 14 User LEDs active High DS10 DS17 1g TI PMBus connector J14 15 User DIP switches active High SW7 1h...

Страница 11: ...s powered through J122 using the 12V AC adapter included with the board J122 is a 6 pin 2 x 3 right angle Mini Fit type connector Caution Do NOT plug a PC ATX power supply 6 pin connector into J122 on...

Страница 12: ...174 J98 Power Controller 1 UCD9240PFC U8 Switching Module PTD08A020W 1 0V at 20A max U10 Switching Module PTD08A020W 2 5V at 20A max U12 Switching Module PTD08A020W PTV12020WAH DC DC Converter MGTHAVC...

Страница 13: ...ail through its corresponding supply jack Caution The external power supply jacks have a maximum current rating of 15A Table 1 1 Onboard Power System Devices Device Reference Designator Description Po...

Страница 14: ...the same PMBus The PMBus connector J14 is provided for use with the TI USB Interface Adapter PMBus pod and associated TI GUI References More information about the power system components used by the M...

Страница 15: ...wer Module The GTX transceiver power module supplies MGTAVCC and MGTAVTT voltages to the FPGA GTX transceivers Three GTX power modules are provided with the ML628 board for evaluation Any one of the t...

Страница 16: ...voltage independently from a bench top power supply The external jacks are shown in Table 1 4 Caution The GTX module MUST be removed when providing external power to the GTX transceiver rails Active...

Страница 17: ...ML628 Board Features and Operation The fan power connections are detailed in Table 1 6 and shown in Figure 1 7 X Ref Target Figure 1 6 Figure 1 6 Active Heatsink Table 1 6 Fan Power Connections Fan W...

Страница 18: ...cable to the JTAG cable connector J1 The FPGA is configured through the System ACE controller by setting the 3 bit configuration address DIP switches SW3 to select one of eight bitstreams stored on a...

Страница 19: ...S6 lights indicating the FPGA is successfully configured X Ref Target Figure 1 8 Figure 1 8 JTAG Chain FMC 2 Connector TDI TDO J441 FMC 1 Connector TDI TDO J290 JTAG Connector TDI TDO J1 J162 J28 J29...

Страница 20: ...t 7 Pressing push button SW2 RESET resets the System ACE controller Reset is an active Low input Configuration Address DIP Switches Figure 1 2 callout 8 DIP switch SW3 selects one of the eight configu...

Страница 21: ...he FPGA pin connections to the LVDS oscillator The 200 MHz differential clock is enabled by placing two shunts P N across J188 header pins 1 3 and 2 4 LVDS Single Ended SMA Global Clock Inputs Figure...

Страница 22: ...itter clock source for the ML628 board The clock module maps to FPGA I O by way of 24 control pins 3 LVDS pairs 1 regional clock pair and 1 reset pin Table 1 12 shows the FPGA I O mapping for the Supe...

Страница 23: ...purpose determined by the user G25 CM_CTRL_1 63 H23 CM_CTRL_2 65 J23 CM_CTRL_3 67 J25 CM_CTRL_4 69 K25 CM_CTRL_5 71 D26 CM_CTRL_6 73 E26 CM_CTRL_7 75 D25 CM_CTRL_8 77 E25 CM_CTRL_9 79 M25 CM_CTRL_10 8...

Страница 24: ...igh Figure 1 2 callout 16 SW5 and SW6 are active High user push buttons that are connected to user I O pins on the FPGA as shown in Table 1 15 These switches can be used for any purpose determined by...

Страница 25: ...access to all GTH transceiver and reference clock pins on the FPGA as shown in Figure 1 10 The GTH transceivers are grouped into six sets of four RX TX lanes Four lanes are referred to as a Quad Note...

Страница 26: ...bly Contact Samtec Inc for other cable assemblies Figure 1 11 A shows the connector pad Figure 1 11 B shows the connector pinout X Ref Target Figure 1 10 Figure 1 10 GTH Quad Locations UG771_c1_10_030...

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