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ML605/SP605 Hardware Tutorial
UG669 (v3.0) March 15, 2011
System Design Flow
Customizing the Embedded Hardware Platform
In this section of the tutorial, the MicroBlaze Processor Subsystem is modified to include
an additional AXI_CDMA and associated benchmarking cores to the system. The
AXI_CDMA core contains two master interfaces (SG engine and data) and a slave
interface. The AXI_CDMA in this tutorial is setup for simple DMA (no SG engine).
The Perf_AXI core starts counting with the first read of the AXI_CDMA master and stops
with the interrupt of the AXI_CDMA core. The core also contains a slave AXI interface for
control/status and counter value registers.
After building the hardware, the benchmarking demonstration application uses a Web
server to display the benchmarking data.
Every data point consists of a data transfer of 1,152,000 bytes by means of the AXI_CDMA
(simple DMA operation which copies data from one area of the main memory to another
area of main memory). The Perf_AXI core (which is added to the system) monitors this
transaction through monitoring signals on the AXI interface master and counts from the
start of the transfer (first read address accepted) to when the core interrupts (transfer is
complete). A block diagram of this system is as shown in
For the ML605 board the AXI_CDMA is running at 151.515151 MHz with a 32-bit interface.
The theoretical throughput on one channel is 606.060606 MB/s. The aggregate throughput
is 1,212 MB/s.
For the SP605 board the AXI_CDMA is running at 100 MHz with a 32-bit interface. The
theoretical throughput on one channel is 400 MB/s. The aggregate throughput is
800 MB/s.
Because both reads and writes are occurring during the AXI_CDMA transfer, the number
represented in the Benchmark Graph is doubled for the total throughput or aggregate
throughput (both read and write).
The steps to customize the MicroBlaze Processor Subsystem include:
1.
Adding IP from the Xilinx IP Catalog, page 26
2.
Connecting the Bus Interfaces, page 29
3.
