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ML40x Getting Started Tutorial
UG083 (v5.0) June 30, 2006
ML40x Demonstrations in Linear Flash
R
ML40
x
Demonstrations in Linear Flash
Description
This demonstration shows the FPGA being configured by an external linear flash device
and a CPLD. This method of download is used in some embedded processor systems
where it is necessary to keep software and bitstream data in one non-volatile device.
Setup
1.
After the bitstreams are programmed into linear flash, shown in
, you can slide the configuration source selector switch (3-position
slide switch) to CPLD Flash.
Optional:
You can change the three leftmost configuration address DIP switches to
different binary values between 0 and 7 to load in a different bitstream from the linear
flash memory.
Note:
The ML402 board supports only four bitstreams in the linear flash memory.
2.
Press the
Prog
button to load bitstream 0 into the FPGA. The serial terminal displays a
message describing how the bitstream was loaded. The LCD also displays a message
indicating that the design was loaded from linear flash.
3.
Now try to program a different bitstream into linear flash. Copy the
hello_char_lcd_hw.bit
bitstream from <
LAB_DIR
> to the CF card into the
XILINX\flash directory. Rename
system0.bit
to
system0.bak
as backup. Then
rename the
hello_char_lcd_hw.bit
file to
system0.bit
.
Note:
On the ML402 board, there might be insufficient space on the CF card to keep the old
ACE file. It might need to be backed up outside the CF card.
4.
Set the configuration address and mode DIP switch (6-position DIP switch) back to
000111
.
5.
Set the configuration source selector switch (3-position slide switch) back to SYS ACE
and press the
System ACE RST
button.
6.
From the Bootloader menu, select option
7
again to start the
Restore CPLD/Flash Images
program.
7.
After the new bitstream is programmed into linear flash, slide the configuration source
selector switch (3-position slide switch) to CPLD Flash again.
8.
Press the
Prog
button to load bitstream 0 into the FPGA. The
hello
message
displayed on the character LCD indicates the new bitstream is stored in flash and
loaded through the CPLD.
