Xilinx CAN FD v2.0, Руководство по эксплуатации продукта

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CAN FD v2.0 10
PG223 December 5, 2018 www.xilinx.com
Chapter 2: Product Specification
Register Space
The CAN FD core requires a 32 KB memory mapped space to be allocated in the system
memory. Division of this addressable space within the core is shown in Table 2-2 .
Note:
The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (
*_wdata
) signal,
and is not impacted by the AXI Write Data Strobe (
*_wstrb
) signal. For write access, both the AXI
Write Address Valid (
*_awvalid
) and AXI Write Data Valid (
*_wvalid
) signals should be asserted
together.
can_clk Clock
I –
CAN clock input. Oscillator frequency tolerance
according to the standard specification.
can_phy_tx PHY O 1 CAN bus transmit signal to PHY.
can_phy_rx PHY I – CAN bus receive signal from PHY.
can_clk_x2 Clock I - This is fully synchronous to the CAN clock and is
a multiple by 2 in frequency.
APB Interface Signals
apb_clk Clock I - APB clock.
apb_resetn Reset I - Active-Low synchronous reset.
apb_pwdata[31:0] APB I - Write data bus.
apb_paddr[14:0] I - Address bus.
apb_pwrite I - Read or Write signaling:
• 0 for Read Transaction.
• 1 for Write Transaction.
apb_psel I - Active-High select.
apb_penable I - Active-High enable.
apb_prdata[31:0] O 0x0 Read Data bus.
apb_pready O 0x0 Active-High ready signal.
apb_perror APB O 0x0 Active-High R/W error signal. Reserved for future
use.
Notes:
1. The core does not support the wstrb signal on the AXI4-Lite interface.
2. The interrupt line is level-sensitive. Interrupts are indicated by the transition of the interrupt line logic from 0 to 1.
3. The AXI4-Lite interface signals and ip2bus_intrevent are synchronous to the s_axi_aclk clock.
Table 2-1: CAN FD Core I/O Signals
Signal Name Interface Type Default Description
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