Wavecom GR64, Примечание к применению, Страница: 10 / 26

2.1.2.4 CTS1 (Clear To Send)
[Wireless CPU® ⇒ Host]
Output signal used to control data flow from the Host UART to the Wireless CPU®
UART.
When hardware flow control is enabled, CTS1 is held low by the Wireless CPU® to
indicate its readiness to accept data from the Host. The Wireless CPU® holds the
CTS1 line high to halt data flow from the Host, for example when the Wireless CPU®’s
UART buffer is full. In order to prevent loss of data, the Host must not send data
while CTS1 is held high. CTS1 is held high immediately preceding, and during sleep
mode.
2.1.2.5 DTR1 (Data Terminal Ready)
[Host ⇒ Wireless CPU®]
DTR1 is an input signal from the Host to indicate a desire to communicate.
DTR1 indicates that the Host is ready or waiting to communicate. When sleep mode is
enabled, DTR1 is used as a mechanism by the Host to request a transition to the sleep
state, or to wake the Wireless CPU® from its sleep state.
A logic low state on DTR1 signals the desire to communicate. A logic high signal
indicates a desire or acknowledgement to allow the sleep state. DTR1 remains high
during the period that the sleep state is active.
2.1.2.6 DSR1 (Data Set Ready)
[Wireless CPU®
⇒
Host]
DSR1 is an output signal from the Wireless CPU® to indicate a desire to communicate.
DSR1 indicates that the Wireless CPU® is ready or waiting to communicate. When
sleep mode is enabled, DSR1 is used as a mechanism by the Wireless CPU® to request
a transition to the sleep state, or to signal to the Host that it has awoken from its
sleep state.
A logic low state on DSR1 signals the desire to communicate. A logic high signal
indicates a desire or acknowledgement to allow the sleep state. DSR1 remains high
during the period that the sleep state is active.
Either the Wireless CPU® or the Host can request and initiate sleep
mode at any time. If the Host initiates sleep, the Wireless CPU® will
not necessarily assume a low-power state. The Wireless CPU®
power state is dependant on what active processes are ongoing.
NOTE
APPLICATION NOTE
GR/GS64 UART Sleep Protocols
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