WJ-8711A DIGITAL HF RECEIVER
CIRCUIT DESCRIPTION
6-7
87IL30
CONTROL
PROCESSOR
(HOST)
CONFIG.
SWITCH
REGISTERS
#1, #2
CONIF*
#2
ADDRESS
DECODER
CONIF*
#1
128KX8
EPROM
ROM*
32KX8
RAM
RAM*
MISC IN*
RECEIVER
STATUS
REGISTER
MUTE
SQL
SQL
RFERR
RF SENSE
PRE/OPT
DIGITAL
SIGNAL
PROCESSOR
IF/AUDIO
DEMULTIPLEX
AND
FILTERING
IF
UP
CONVERSION
25 kHz IF
MULTIPLEXED
ANALOG
IF AND AUDIO
ANALOG
RECONSTRUCTION
D/A
IF/AUDIO
SERIAL DATA
DATA
RECONSTRUCTION
TIMING
DAC CLK
DACLE
ASWIF
ASWAUD
DIGITIZED SERIAL
IF DATA
FRAME
SYNCHRONIZATION
SERIAL DATA
CLOCK
RECONSTRUCTED
ANALOG SECTION
DIGITAL SIGNAL
PROCESSING SECTION
IF
DIGITIZER
A/D
DATA BUS
RF DATA
PARALLEL TO
SERIAL OUTPUT
RF DATA
PARALLEL TO
SERIAL OUTPUT
DATA BUS
RFDEN*
MISC OUT*
RFDEN*
RFCLK/J4 PIN 11
RFDATA/J4 PIN 10
RF0/J4 PIN 9
RF1/J4 PIN 8
RF2/J4 PIN 7
SYNCHRONIZED
CLOCK
DISTRIBUTION
SRF DATA
SYNCHRONIZATION
RF
INT*
RF
INT*
2 MHz
CLOCK
8 MHz
CLOCK
40 MHz
J4 PIN 23
ADDRESS BUS
ADDRESS BUS
RFGC
J4 PIN 15
RFGC
SIG. STR
SQL
MUTE
RSSI/
SQL OUT
MUTE IN
AUDIO LINE B
DC AUDIO
SPEAKER AUDIO
AUDIO LINE A
IF OUT
A2J1
REAR
PANEL
TB1
+
-
RF ERR
RF SENSE
PRE/OPT
RF ERR J4 PIN 8
RF SENSE J4 PIN 14
PRE/OPT J4 PIN 12
CONTROL
INTERFACE
A1A1P1
RS-232
INTERFACE
A2J3
CSMA
INTERFACE
A2J2
CONTROL AND INTERFACE SECTION
SIG.STR.
RFGC
430 kHz
J4 PIN 17
Figure 6-3. Type 797214-1 Digital Assembly Functional Block Diagram
Courtesy of http://BlackRadios.terryo.org
Содержание WJ-8711A
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