Counter 750-404
:$*2
Ç
,
2
Ç
6<67(0
12
Structure of Input and Output data
The input data contain the CLOCK frequency as a binary value. The representation
depends on the RANGE_SEL bits in the CONTROL byte. Even the method of
measuring is selected via these bits. The following table illustrates the different modes.
5$1*(B6(/ 5$1*(B6(/ 0HWKRGRIPHDVXUHPHQW
5HSUHVHQWDWLRQRIPHDVXULQJYDOXH
,QWHJUDWLRQRYHUSHULRG
)UHTXHQF\LQ
+]
,QWHJUDWLRQRYHUSHULRGV
)UHTXHQF\LQ
+]
,QWHJUDWLRQRYHUSHULRGV
)UHTXHQF\LQ
+]
,QWHJUDWLRQRYHUSHULRGV
)UHTXHQF\LQ+]
Attention:
When a new frequency range is requested, the application has to wait for valid data until
the RANGE_SEL ACK bits contain the new frequency range. The maximum delay can
be calculated using the following formula
number of periods to be integrated
actual frequency
If the gate is enabled the input data contains the last valid frequency value. In this state
the application cannot request a new range.
The valid frequency range stretches from 0.1 Hz (100
D
) up to
10 kHz (100000
D
).
To recognize static CLOCK signals, a watchdog timer is implemented. The default
value for the timer is 10s. The timer resets on every Power On.
The application is able to change the watchdog time during operation by using the
CONTROL byte.
This can be initiated by writing the corresponding value into the output bytes
OUTPUT_DATA 1 and OUTPUT_DATA 0 before setting the T
VD
REQ bit in the
CONTROL byte.
The success of the parameter transfer is acknowledged by the module via the T
VD
ACK
bit in the STATUS information.
Attention:
The range of the watchdog timer stretches from 0 to 16383ms (0x0000
H
to 0x3FFF
H
) in
steps of 1ms per digit.
Values which raise the permitted range of the watchdog timer are masked with 0x3FFF.
If the maximum possible frequency of the different ranges is raised (see the table with
maximum frequency ratings), the module will return the non valid data 0xFFFFFFFF
H
.
T
Dmax
= 2 *
