Feldbus-Koppler/-Controller • 79
Fieldbus Controller 750-806
WAGO-I/O-SYSTEM 750
DeviceNet
3.2.5.3.2 Absolute Addressing
The CPU has direct access to the bus terminal data through absolute addresses.
Addressing begins with the address 0 both with inputs and outputs. The corre-
sponding addresses for bits, bytes and double words (DWord) are derived
from the word addresses.
The structure of the process image is described in chapter 3.2.4 Process Image.
Addressing is done in this structure.
Input data
%IW0
|
%IW
n
word-orientated data
%I
n+1
|
%I
n+m
bit-orientated data
Output data
%QW0
|
%QW
n
word-orientated data
%Q
n+1
|
%Q
n+m
bit-orientated data
3.2.5.3.3 Calculate Addresses
The word address is the basis for calculation (word).
Bit Address
Word address .0 to .15
Byte Address
1st byte:
2 x Word address
2nd byte: 2 x Word a 1
DWord Address
lower section: Word address (even numbers) / 2
upper section: Word address (odd numbers) / 2, rounded off
3.2.5.3.4 Address Range for I/O Module Data
Data size
Address range I/O module data
Bit
0.0
...
0.7
0.8
...
0.15
1.0
...
1.7
1.8
...
1.15
...
254.0
...
254.7
254.8
...
254.15
255.0
...
255.7
255.8
...
255.15
Byte
0
1
2
3
...
508
509
510
511
Word
0
1
...
254
255
DWord
0
...
127
