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Страница 1: ...utilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stoc...

Страница 2: ...UAL PORT MEMORY PC 104 AND CACHE PRODUCT MANUAL DOCUMENT NO 500 107487 000 C Revised July 21 1997 VME MICROSYSTEMS INTERNATIONAL CORPORATION 12090 SOUTH MEMORIAL PARKWAY HUNTSVILLE AL 35803 3308 205 8...

Страница 3: ...Works Foundation IOWorks man figure IOWorks Manager IOWorks Server MAGICWARE MEGAMODULE PLC ACCELERATOR ACCELERATION Quick Link Soft Logic Link SRTbus TESTCAL The Next Generation PLC The PLC Connectio...

Страница 4: ...ceding transaction 3 The preceding transaction was a D64 slave read from the failing slave 4 The current transaction must be a D64 transaction 5 The preceding transaction exhibits a local read ahead c...

Страница 5: ...CHANGE NUMBER VME MICROSYSTEMS INT L CORP 12090 South Memorial Parkway Huntsville AL 35803 3308 205 880 0444 REV LTR PAGE NO iii DOC NO 500 107487 000 C A 01 25 96 Release 96 0110 B 05 01 96 Cover an...

Страница 6: ...es a definite safety hazard KEEP AWAY FROM LIVE CIRCUITS Operating personnel must not remove product covers Component replacement and internal adjustments must be made by qualified maintenance personn...

Страница 7: ...rminal marked with this symbol must be connected to ground in the manner described in the installation operation manual Frame or chassis terminal A connection to the frame chassis of the equipment whi...

Страница 8: ...TALLATION AND SETUP 2 1 SECTION 1 INTRODUCTION 2 1 SECTION 2 UNPACKING PROCEDURES 2 2 SECTION 3 HARDWARE SETUP 2 3 SECTION 4 LED STATUS DEFINITION 2 5 SECTION 5 INSTALLATION 2 5 SECTION 6 FRONT PANEL...

Страница 9: ...AT INTERRUPTS 3 8 SECTION 5 ENHANCED I O PORTS 3 12 SERIAL PORTS 3 13 PARALLEL PORT 3 13 SECTION 6 VIDEO GRAPHICS ADAPTER 3 14 SECTION 7 PC 104 EXPANSION SITE 3 15 CHAPTER 4 VMEbus FUNCTIONS 4 1 SECTI...

Страница 10: ...25 SECTION 6 VMEbus INTERRUPT HANDLING 4 26 Software Interrupts 4 30 Interrupt on BERR 4 30 Periodic Timer Interrupt 4 30 Interrupt Processing 4 31 SECTION 7 VMEbus INTERRUPTER 4 33 SECTION 8 VMEbus R...

Страница 11: ...4 57 INTERRUPT ACKNOWLEDGE REGISTER DETAILS 4 58 VIC REGISTER DETAILS 4 58 VMEbus Interrupter Interrupt Control Register 4 59 VMEbus Interrupt Control Registers 4 60 DMA Status Interrupt Control Regis...

Страница 12: ...Registers 4 95 System Reset Register 4 96 INTERPROCESSOR COMMUNICATIONS REGISTERS 4 96 Interprocessor Communications Switch Register 4 97 Interprocessor Communication Registers 4 98 VIC Version Regis...

Страница 13: ...B 1 SECTION 1 INTRODUCTION B 1 SECTION 2 ETHERNET SOFTWARE COMPATIBILITY B 2 SECTION 3 ETHERNET DRIVER SOFTWARE B 3 SECTION 4 ETHERNET DIAGNOSTIC SOFTWARE B 3 SECTION 5 TECHNICAL DETAILS B 5 APPENDIX...

Страница 14: ...AND MENU ITEMS D 8 MAIN MENU D 8 System Time D 9 System Date D 9 Diskette A B D 9 Video System D 9 Large Disk Mode D 9 System Memory Extended Memory D 9 IDE Adapter 0 Master IDE Adapter 0 Slave Sub m...

Страница 15: ...ETUP Prompt D 20 POST Errors D 20 Floppy Check D 20 Summary Screen D 20 KEYBOARD FEATURES D 21 NumLock D 22 Key click D 22 Keyboard Auto Repeat Rate D 22 Keyboard Auto Repeat Delay D 22 SECTION 6 EXIT...

Страница 16: ...3 12 Figure 4 1 VMIVME 7487A VMEbus Functions 4 3 Figure 4 2 VMEbus Interface Block Diagram 4 4 Figure 4 3 VLIC Block Diagram 4 5 Figure 4 4 Real Mode VMEbus Access 4 9 Figure 4 5 Protected Mode VMEbu...

Страница 17: ...Figure A 9 Serial Connector Pinouts A 10 Figure A 10 Video Connector Pinout A 11 Figure A 11 VMEbus Connector Diagram A 12 Figure B 1 Location of the Ethernet Mezzanine B 2 Figure C 1 Flash Mezzanine...

Страница 18: ...500 107487 000 LIST OF FIGURES VMIVME 7487A PRODUCT MANUAL xvi Figure D 9 PhoenixBIOS Keyboard Features Sub menu D 21 Figure D 10 PhoenixBIOS Exit Menu D 23...

Страница 19: ...ommon Supported Graphics Video Resolutions 3 14 Table 4 1 Protected Mode VMEbus Address Modifiers 4 11 Table 4 2 Slave Access Memory Map 4 22 Table 4 3 Interrupt Priorities 4 26 Table 4 4 Interrupt Le...

Страница 20: ...500 107487 000 LIST OF TABLES VMIVME 7487A PRODUCT MANUAL xviii Table D 2 PhoenixBIOS Fixed Disk Table D 12 Table D 3 PhoenixBIOS Status and Error Messages D 25...

Страница 21: ...a standard PC AT It executes a PC AT type power on self test then boots up MS DOS Windows OS 2 NextStep XENIX or any other PC AT compatible operating system Its keyboard and video console interaction...

Страница 22: ...an I O bus that is completely independent from the memory bus Every effort has been made in the manual to clarify this by referring to registers and logical entities in I O space by pre xing I O addre...

Страница 23: ...VMEbus controllers all of which combine a standard PC AT architecture with the ability to control VMEbus slave boards Figure 1 1 VMIVME 7487A Board View J7 J6 Keyboard Port Parallel Port LPT1 IDE Hard...

Страница 24: ...support products for the PC AT compatible VMEbus controller line The VMIVME 7450 is a dual slot module which holds one 3 5 inch oppy drive and one 3 5 inch hard drive The VMIVME 7451 is a single slot...

Страница 25: ...cessor Programmer s Reference Manual and the Intel 486DX Microprocessor Data Book Intel Corporation Literature Sales Dept P O Box 58130 Santa Clara CA 95052 8130 VMEbus Speci cation Rev C1 and The VME...

Страница 26: ...igh speed external level 2 write back cache Super VGA video 1 Mbyte of video DRAM Scan resolutions up to 1280 x 1024 noninterlaced Color resolutions up to 16 5 million TruColor Battery backed clock ca...

Страница 27: ...500 107487 000 PC ATFEATURES VMIVME 7487A PRODUCT MANUAL 1 7 Figure 1 2 VMIVME 7487A Partial Block Diagram...

Страница 28: ...ted Table 1 1 PC AT I O Features I O FEATURE MS DOS IDENTIFIER PHYSICAL ACCESS Two High Speed Serial Ports 16550 compatible RS 232C COM1 COM2 Front Panel RJ45 male X 2 One Enhanced Bidirectional Paral...

Страница 29: ...Figure 1 3 shows the VMIVME 7487A functions in a typical VMEbus system The VMIVME 7487A is a versatile single board solution for VMEbus control with familiar PC AT operation 80486 CPU DTB MASTER VMIVM...

Страница 30: ...CHAPTER 1 INTRODUCTION 500 107487 000 1 10 VMIVME 7487A PRODUCT MANUAL...

Страница 31: ...STATUS DEFINITION 2 5 SECTION 5 INSTALLATION 2 5 SECTION 6 FRONT PANEL CONNECTORS 2 6 SECTION 7 PC 104 EXPANSION SITE 2 7 SECTION 8 BIOS SETUP 2 8 SECTION 9 CONFIGURING OPERATING SYSTEMS 2 8 SECTION...

Страница 32: ...A CONDUCTIVE SHUNT UNUSED BOARDS SHOULD BE STORED IN THE SAME PROTECTIVE BOXES IN WHICH THEY WERE SHIPPED Upon receipt any precautions found in the shipping container should be observed All items sho...

Страница 33: ...PC 104 Bus J2 PC 104 Expansion Site VMIVME 7487A COM1 Port RS 232 COM2 Port RS 232 Power and Status Indicators Reset Switch Monitor Port VGA Ethernet Port E2 E1 E9 E8 E11 E4 E3 E6 E7 E15 E16 E16 Syst...

Страница 34: ...el Port Interrupt 2 3 2 3 Disabled Disabled 2 3 Default 1 2 Default I O Address 378 37F Standard LPT1 IRQ7 1 2 2 3 I O Address 278 27F Standard LPT2 IRQ5 1 2 1 2 I O Address 3BC 3BF Alternate LPT1 IRQ...

Страница 35: ...er is applied to the board SECTION 5 INSTALLATION DO NOT INSTALL OR REMOVE BOARD WHILE POWER IS APPLIED The VMIVME 7487A conforms to the VMEbus physical speci cation for a 6U x 4HP dual Eurocard dual...

Страница 36: ...t all needed peripherals to the front panel Each connector is clearly labelled on the front panel and detailed pinouts are in Appendix A Minimally a keyboard and a monitor are required 6 Apply power t...

Страница 37: ...hat the attachment hardware shown the nuts screws and standoffs should be included with the PC 104 board and are not included with the VMIVME 7487A Con guration information for PC 104 accessories shou...

Страница 38: ...including MS DOS PC DOS DR DOS Microsoft Windows and Windows NT IBM s OS 2 UNIX versions designed to run on Intel microprocessors and UNIX variants such as XENIX In general any operating system desig...

Страница 39: ...ccesses just as if they were inside the actual VMEbus Window Operating systems vary widely in their implementation of address range exclusion Indeed some operating systems without complex memory manag...

Страница 40: ...lusion is necessary for the Protected Mode VMEbus Window The latter is true because EMM386 EXE will not attempt to use memory above that reported by the BIOS which will always be below the beginning o...

Страница 41: ...Translation Look aside Buffers Segmentation Unit Descriptor Registers Limit and Attribute PLA Cache Unit 8 Kbyte Unified Cache 64 bit Shifter 32 bit Register File ALU Barrel FPU Register File Control...

Страница 42: ...M EMS expanded memory with the proper driver like Microsoft s EMM386 or QEMM from Quarterdeck Of ce Systems If expanded memory is used the recommended 64 Kbyte page frame is at D0000 See Chapter 2 for...

Страница 43: ...ted Mode VMEbus Windows 0200 0000 42FF FFFF 1040 Mbytes Reserved 0010 0000 01FF FFFF 31 Mbytes Reserved for On Board Extended Memory not filled on all systems REAL MODE F0000 FFFFF 64 Kbytes ROM BIOS...

Страница 44: ...rcuitry decodes only 10 of the I O address lines going out to the expansion bus This limits the PC 104 address space to 1024 locations 000 3FF The VMIVME 7487A incorporates all standard I O peripheral...

Страница 45: ...yboard Speaker Eqpt Config Intel 8042 Compatible 065 06F 11 Reserved 070 071 2 ACC Micro 2168 Chip Real Time Clock NMI Mask 072 07F 14 Reserved 080 08F 16 ACC Micro 2168 Chip DMA Page Registers 090 09...

Страница 46: ...le 2FF 31F 33 Reserved by VMIC 320 36F 80 User I O 370 377 8 Super I O Chip Secondary Floppy Disk Controller E9 E8 378 37F 8 Super I O Chip LPT1 Enhanced Parallel I O EPP ECP Compatible E6 E7 default...

Страница 47: ...ts are reserved for the listed functions they are not implemented on the VMIVME 7487A They are listed here to make the user aware of the standard PC AT usage of these ports These jumpers can affect wh...

Страница 48: ...page 3 9 details the vectors in the interrupt vector table Table 3 3 PC AT Hardware Interrupts IRQ AT FUNCTION COMMENTS NMI Parity Errors Must be enabled in BIOS Setup Used by VMIVME 7487A VMEbus Int...

Страница 49: ...IRQ2 BIOS Reserved Invalid Task State Segment 0B 11 IRQ3 COM2 Serial I O Segment Not Present 0C 12 IRQ4 COM1 Serial I O Stack Segment Overrun 0D 13 IRQ5 Fixed Disk Controller or VMEbus Interrupts alt...

Страница 50: ...ute Disk Read Same as Real Mode 26 38 DOS Absolute Disk Write Same as Real Mode 27 39 DOS ProgramTerminate Stay Resident Same as Real Mode 28 40 DOS Keyboard Idle Loop Same as Real Mode 29 41 DOS CON...

Страница 51: ...the IBM PC XT In the IBM PC XT computers only eight interrupt request lines exist numbered from IRQ0 to IRQ7 at the PIC The IBM PC AT computer added eight more IRQx lines numbered IRQ8 to IRQ15 by ca...

Страница 52: ...or Super I O chip This chip provides the VMIVME 7487A with a oppy drive controller IDE hard drive interface two serial ports and one parallel port While the oppy and hard drive interfaces are standard...

Страница 53: ...depth of 10 By not taking advantage of the transmit FIFO the Windows driver incurs more processor overhead and may not be reliable beyond 9600 baud especially while multitasking Fortunately many thir...

Страница 54: ...orts VESA high resolution and extended video modes Table 3 6 shows the popular graphics video modes supported by the Cirrus Logic video chip Note that not all VGA monitors support resolutions and refr...

Страница 55: ...rs for display devices PCMCIA adapters Ethernet and SCSI interfaces and other I O functions VMIC s VMIVME 7432 PC 104 to ISA Adapter is designed speci cally to mate with the VMIVME 7487A allowing it t...

Страница 56: ...CHAPTER 3 PC AT FUNCTIONS 500 107487 000 3 16 VMIVME 7487A PRODUCT MANUAL...

Страница 57: ...ODUCTION This chapter serves as both a programmer s instruction manual and a reference guide to the VMEbus interface of the VMIVME 7487A The chapter begins with sections concerning general VMEbus inte...

Страница 58: ...ows OS 2 and XENIX on the other hand run in Protected Mode and can utilize all available extended memory The VMIVME 7487A can access the VMEbus in Real Mode or Protected Mode As a VMEbus interrupt pro...

Страница 59: ...n Protected Mode 16 Mbytes at a time VMEbus INTERFACE HARDWARE The VMIVME 7487A VMEbus hardware interface is based on the Cypress VIC64 VMEbus Interface Controller hereafter referred to as the VIC and...

Страница 60: ...VLIC block VIC to Local bus Interface Circuitry Figure 4 2 VMEbus Interface Block Diagram The CPU interface of the VIC was designed to be part of a Motorola 68030 system An interface is required to co...

Страница 61: ...80486 bus between the VIC and the ACC Micro 2168 The VIC requests the local bus when a VMEbus slave access to the dual ported DRAM is requested The 2168 requests the local bus when a DRAM refresh is...

Страница 62: ...ce registers are in I O space and consequently are accessed using 80486 I O instructions The VMIVME 7487A contains nine System Registers three Interrupt Acknowledge Registers and 58 VIC Registers Of t...

Страница 63: ...0 of the I O address must be set Address bit A8 must also be set to access the Interrupt Acknowledge Registers Section 13 details the location and function of the Interrupt Acknowledge Registers SECTI...

Страница 64: ...E Enable bit is set in the General Purpose Command Register The desired address modi er code is contained in the VIC Address Modi er Source Register The upper address bits are contained in the Extende...

Страница 65: ...u s 0 X AM5 AM4 AM3 AM2 AM1 AM0 D7 D6 D5 D4 D3 D2 D1 D0 A31 A30 A29 A28 A27 A26 A25 A24 D15 A23 A22 A21 A20 A19 A18 A17 A16 D0 B U F F E R 80486 80486 REAL MODE 80486 A19 A16 1110 E GP_COMMAND VME_EN...

Страница 66: ...his sets the upper VMEbus address bits as shown in Figure 4 4 on page 4 9 effectively controlling which 64 Kbyte segment of VMEbus addressing space appears in the Real Mode VMEbus Window 5 Perform a m...

Страница 67: ...1 A32 Supervisory program 0 1 0 1 1 0 1 1 A32 Supervisory data 0 1 0 1 0 1 1 1 A32 Nonprivileged program 0 1 0 1 0 0 1 1 A32 Nonprivileged data 0 1 0 0 1 1 1 1 User defined VIC AMSR 5 0 0 1 0 0 1 1 1...

Страница 68: ...C by setting the VIC Enable bit V M E b u s A31 A30 A29 A28 A27 A26 A25 A24 D15 B U F F E R 80486 80486 PR OTECTED MODE 80486 A31 A30 01 GP_COMMAND VME_EN 1 A23 A1 D31 00 A23 A1 D31 D0 A31 A24 AM5 AM0...

Страница 69: ...g space appears in the Protected Mode VMEbus Window For Protected Mode operation bits 0 7 of the register are not used 5 Perform memory access at an address between 4300 0000 and 7FFF FFFF depending u...

Страница 70: ...he ve mailbox registers The other ICR registers allow a VMEbus master to gain status information about the VMIVME 7487A See page 4 98 for a complete description of all Interprocessor Communications Re...

Страница 71: ...ss the resource The mask register is used to de ne an address range that is used to access the resource As Figure 4 6 shows the LSB CY7C964 has a MATCH output which is connected to the VIC ICFSEL inpu...

Страница 72: ...s The upper register bits of the Slave A16 Address Compare and Mask registers correspond to VMEbus address bits A8 A15 see the register description on page 4 57 Note that register bits D7 D0 are not u...

Страница 73: ...ion resources prior to the Mailbox Enable bit being set will result in a VMEbus BERR provided that a bus timeout module is enabled somewhere in the system Example Program VIC ICR registers to reside a...

Страница 74: ...resources are not used to cause interrupts into the VMIVME 7487A 3 Initialize the Slave A16 Address Compare and Slave A16 Address Mask Registers Program the desired address and range Note that the Sl...

Страница 75: ...by the MSB or NMSB CY7C964 address compare and mask registers The VIC contains slave select control registers SS0CR0 SS0CR1 SS1CR0 SS0CR1 which allow the user to de ne VMEbus address modi er codes to...

Страница 76: ...tes of on board DRAM to A32 VMEbus address 1200 0000 1 Write 0x12XX data to the Slave A32 A24 Address Compare register 2 Write 0x00XX to the Slave A32 A24 Address Mask register 3 Initialize VIC SS0CR0...

Страница 77: ...ogram desired address and range Note that the Slave A32 A24 Address Compare must always be programmed prior to the Slave A32 A24 Address Mask register This is required since an access to the Slave A32...

Страница 78: ...YSTEM EITHER THE VMIVME 7487A BUS TIMEOUT MODULE OR ANOTHER BUS TIMEOUT MODULE ELSEWHERE Table 4 2 Slave Access Memory Map Local Address Resource 0200 0000 FFFF FFFF NOT ACCESSIBLE 0010 0000 01FF FFFF...

Страница 79: ...us A24 space if the Slave A32 A24 Address Mask system register is cleared Setting bit 0 of the Slave A32 A24 Address Mask register increases the memory allocation to 128 Kbytes Setting the Slave A32 A...

Страница 80: ...4 24 VMIVME 7487A PRODUCT MANUAL Figure 4 8 Slave Addressing Detail V M E b u s B U F F E R A31 A25 7 CY7C964 CY7C964 CY7C964 VIC64 A31 A24 A23 A16 A23 A16 A15 A8 A15 A8 A7 A0 A7 A1 DS0 DS1 V 4 8 7 L...

Страница 81: ...RRS or BCLR operation Single level arbitration is obtained by programming the RCR for PRI and setting all requesters to level 3 In the RRS scheme arbitration priority is assigned on a rotating basis w...

Страница 82: ...ut timer This is desirable since the VMIVME 7487A local DRAM controller requires the local bus every 15 6 s to refresh the DRAM Therefore to properly signal a bus error for master operations caused by...

Страница 83: ...nterrupt vectors or IDs associated with them This vector or ID is supplied by the VIC during the interrupt acknowledge cycle The VIC determines which interrupt level is being acknowledged and then iss...

Страница 84: ...ding level In the event that the highest pending interrupt is a VMEbus interrupt IRQ7 IRQ1 the register read will initiate a VMEbus Interrupt Acknowledge cycle The returned ID value will be the ID rea...

Страница 85: ...rors and off board parity errors The off board parity error was designed to allow ISA boards which contained memory to ag the motherboard processor in the event of a parity error This is accomplished...

Страница 86: ...6 CPU does not directly support bus error conditions Consequently when the 80486 accesses the VMEbus the cycle will terminate when either a DTACK or BERR is activated If a VMEbus access is terminated...

Страница 87: ...ontrast the PC AT architecture de nes non NMI interrupts to be edge sensitive To ensure that the PC AT hardware properly recognizes VIC interrupts VIC level interrupts are converted to edges by perfor...

Страница 88: ...Interrupt Processing for IRQ11 End ISR Start ISR Read IRQ11_ID Use vector to branch to specific ISR Write EOI to 8259 pic ISR Ready INIT IRQ11 Install vector 11 Set up VIC64 interrupt sources for lev...

Страница 89: ...nowledged by an off board interrupt handler the VIC supplies the vector associated with that interrupt provided the VMIVME 7487A IACKIN signal is active The VMIVME 7487A can be programmed to interrupt...

Страница 90: ...he VIC allows the user to program which VMEbus bus request signal BR3 BR0 will be used to request the bus This is programmed in the VIC ARCR register The default setting of the register after system r...

Страница 91: ...0486 LOCK signal is connected to the RMC input of the VIC When the VIC detects a master VMEbus request by the VMIVME 7487A and the activation of the RMC input a VMEbus RMW cycle is performed Note that...

Страница 92: ...tiprocessing semaphore that is located in the VMIVME 7487A dual port RAM The semaphore should be accessed by the 80486 using locked instructions The semaphore may be accessed by another VMEbus master...

Страница 93: ...g bits 3 0 of the BTCR with a value equal to 1 or more For slave BLT accesses to the VMIVME 7487A the VIC becomes the VMIVME 7487A local bus master To ensure that the DRAM controller gains access to t...

Страница 94: ...ined in EXT_STD_ADDR A15 A0 of the slave BLT address is the offset address used during the Real Mode VMEbus Window access The local bus address is the 32 bit value written to the Real Mode VMEbus Wind...

Страница 95: ...64 FUNCTIONS A VMIVME 7487A with the VME64 installed may transfer 64 bits at a time using VME64 MBLT block transfers MASTER VME64 OPERATION As de ned in Section 13 the BTDR register has additional bit...

Страница 96: ...LWORD select which byte s within the group are accessed Table 4 5 depicts the Even Odd Byte assignments to the VMEbus data lines It is important to note the major byte ordering differences between the...

Страница 97: ...memory with the least signi cant byte in the lowest byte address thus earning the name little endian ordering The VMIVME 7487A uses an Intel 80486 microprocessor which uses little endian byte ordering...

Страница 98: ...signi cant byte in the highest byte address in memory while its most signi cant byte is written to the lowest address The converse is true during read operations the data in the lowest byte address is...

Страница 99: ...ld be incorrectly assumed to be the least signi cant while it is actually the most signi cant The problem cannot be solved by simply connecting the 80486 to the VMEbus with its byte lanes crossed For...

Страница 100: ...4 6 Byte Swap Modes BIG ENDIAN BIT STATUS SIZE OF TRANSFER SWAP MODE X single byte byte swap 0 word two bytes byte swap 0 longword four bytes word swap 1 word two bytes direct 1 longword four bytes d...

Страница 101: ...re Master Slave Byte Swapping On the VMIVME 7487A byte ordering can be programmed for either big endian or little endian in both directions that is whether the VMIVME 7487A is a VMEbus master or a VME...

Страница 102: ...sters have a xed location I O 140 through I O 14F The location of the Interrupt Acknowledge and VIC Registers are determined by the value in the VIC Base Register a System Register at the xed address...

Страница 103: ...Address Mask 4 57 SL_A32_A24_MAS K Word Write 14A A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 Slave A16 Address Compare 4 57 SL_A16_ADDR Word Write 14C A15 A14 A13 A12 A11 A10 A9...

Страница 104: ...al Interrupt Control 3 4 62 LICR3 42F LIRQ3 Mask High Polarity Edge Enable Auto vector LIRQ3 State IPL Value Local Interrupt Control 4 4 62 LICR4 433 LIRQ4 Mask High Polarity Edge Enable Auto vector L...

Страница 105: ...nterrupt Vector Base 1 4 70 VIVBR1 487 IRQ1 Status ID Vector VMEbus Interrupt Vector Base 2 4 70 VIVBR2 48B IRQ2 Status ID Vector VMEbus Interrupt Vector Base 3 4 70 VIVBR3 48F IRQ3 Status ID Vector V...

Страница 106: ...Access SLSEL1 D32 Enable SLSEL1 Address Space Con guration SLSEL1 Local Transfer Mode Slave Select 1 Control Register 1 4 89 SS1CR1 4CF SLSEL1 Timing Field 1 SLSEL1 Timing Field 0 Release Control 4 9...

Страница 107: ...01 ICGS2S 15 Any write access sets ICGS2 privileged access only Clear ICGS3 Switch 4 101 ICGS3C 16 Any write access clears ICGS3 privileged access only Set ICGS3 Switch 4 101 ICGS3S 17 Any write acces...

Страница 108: ...6 D5 The 80486 processor uses Intel s little endian method for transferring a multiple byte group between its internal registers and external memory The VMEbus however expects Motorola s big endian me...

Страница 109: ...esses to the VMIVME 7487A Bit 4 controls VMIVME 7487A slave access as an A32 Extended device When set the VMIVME 7487A may be accessed using A32 Extended VMEbus addressing mode Bit 0 functions similar...

Страница 110: ...1 controls master VMEbus access While this bit is clear the default state after powerup or reset the VMIVME 7487A cannot access the VMEbus as a master While VMEbus access is disabled the VMIVME 7487A...

Страница 111: ...write only byte register at I O address 141 This register determines the base I O address of both the VIC and the Interrupt Acknowledge Registers All active bits in this register are cleared on power...

Страница 112: ...rt into an output only con guration VIC Base Register VIC Enable Bit D0 When set the VIC Enable bit allows the VIC chip to be accessed at the base address determined by the A11 A15 eld described above...

Страница 113: ...r more details regarding VMEbus access in Protected Mode Onboard Video Status Register The Video Status Register indicates whenever the onboard video controller has been selected or a PC 104 video con...

Страница 114: ...e IRQ11 and IRQ12 signals can only originate from the VIC but the NMI can have other origins therefore special care must be taken in the NMI ISR to ensure that the VIC is the source of the pending NMI...

Страница 115: ...terrupt Control Register The VMEbus Interrupter Interrupt Control Register VIICR is a read write byte register at VIC offset I O address 403 This register provides enabling and IPL level encoding for...

Страница 116: ...e Section 6 on page 4 26 for a detailed discussion of interrupt handling procedures VMEbus Interrupt Control Registers IRQ Mask bit D7 When this bit is clear the VIC acts as a VMEbus interrupt handler...

Страница 117: ...value of F8 upon powerup or hard reset DMA Status Interrupt Control Register DMA Status Interrupt Mask bit D7 When this bit is clear the VIC signals a local interrupt at the completion of any VIC loc...

Страница 118: ...r the VIC is enabled to handle the corresponding local interrupt asserted on the LIRQ1 7 signals Local Interrupt Control Registers High Polarity bit D6 When this bit is set the VIC responds to interru...

Страница 119: ...indicates the LIRQ1 7 signal is asserted at the VIC Local Interrupt Control Registers IPL Value bit field D2 D0 This value is inverted and driven onto the IPL lines when a local interrupt is presented...

Страница 120: ...gister The ICMS Interrupt Control Register ICMSICR is a read write byte register at VIC offset I O address 447 This register provides enabling and IPL encoding for the four module switch interrupts Th...

Страница 121: ...for the error group interrupts Error Group Interrupt Control Register ACFAIL Interrupt Mask bit D7 When this bit is clear the VIC generates a local interrupt when ACFAIL is detected as asserted D7 D4...

Страница 122: ...ver SYSFAIL is detected asserted Error Group Interrupt Control Register IPL Value bit field D2 D0 This value is inverted and driven onto the IPL signals when an error group interrupt is acknowledged I...

Страница 123: ...upt Vector Base Register The ICMS Interrupt Vector Base Register ICMSIVBR is a read write byte register at VIC offset I O address 453 This register provides the status ID vector for the module switch...

Страница 124: ...ser de nable and are used with bits 2 0 to provide a unique local interrupt status ID vector Local Interrupt Vector Base Register Local Interrupt Number bit field D2 D0 This read only value indicates...

Страница 125: ...rupt acknowledge cycle Interprocessor Communications Registers Please refer to the Interprocessor Communications Registers detailed beginning on page 4 96 VMEbus Interrupt Request Status Register The...

Страница 126: ...MEbus Interrupt Vector Base Registers The VMEbus Interrupt Vector Base Registers VIVBR are read write byte registers at VIC offset I O addresses 487 48B 48F 493 497 49B 49F corresponding to IRQ1 IRQ7...

Страница 127: ...de all settings here except the 4 s value See the discussion concerning the system controller functions on page 4 7 Transfer Timeout Register TTR VIC offset I O 4A3 D7 D6 D5 D4 D3 D2 D1 D0 VMEbus Time...

Страница 128: ...bit is set the local bus timer will include waiting for VMEbus acquisition When clear the local bus timer will stop and reset when the VMEbus is requested D4 D3 D2 Local Bus Timeout s 0 0 0 4 0 0 1 16...

Страница 129: ...time is speci ed by the formula n 1 15 625 ns This value must be set to maximum all bits set when performing slave RMW cycles or BLT transfers on the VMIVME 7487A Local Bus Timing Register Minimum DS...

Страница 130: ...all active bits in this eld must be set Block Transfer Definition Register D64 Boundary Crossing Enable bit D7 When set the VIC64 assumes D64 transfers are aligned to a 2 Kbyte boundary Block Transfer...

Страница 131: ...LT transfers on the VMIVME 7487A Interface Configuration Register The Interface Con guration Register ICR is a read write byte register at VIC offset I O address 4AF This register controls various fea...

Страница 132: ...or the VMIVME 7487A and is the only condition possible for slave accesses When performing slave accesses bit 4 should always be clear Interface Configuration Register Metastability Interval bit D2 Whe...

Страница 133: ...ster Configuration Register Arbitration Mode bit D7 When this bit is set the VIC performs priority VMEbus arbitration When clear the VIC performs round robin arbitration This bit is only relevant when...

Страница 134: ...odes during VMEbus slave cycles This register is initialized to a value of 00 upon powerup or hard reset Address Modifier Source Register AM2 0 Option bit D7 When this bit is set the VIC issues the AM...

Страница 135: ...andard VMEbus AM codes are used Bus Error Status Register The Bus Error Status Register BESR is a read write byte register at VIC offset I O address 4BB This register provides BERR LBERR self access V...

Страница 136: ...e VIC LBERR asserted to the VIC Once set this bit must be cleared manually Local bus errors will never occur in the current VMIVME 7487A configuration D5 VMEbus Bus Error This bit is set when a VMEbus...

Страница 137: ...copy of bit 6 of the BESR Local bus errors cannot occur in the current VMIVME 7487A con guration therefore this bit will remain clear DMA Status Register BERR During DMA bit D2 This bit when set indi...

Страница 138: ...his local interrupt LICR2 must be enabled The frequencies for this interrupt are given below Slave Select 0 Control Register 0 Supervisory Access bit D5 When this bit is set SLSEL0 slave accesses are...

Страница 139: ...ocal bus transfers D4 D32 Enable Bit Function D32 Slave Access Control 0 D32 slave operations are disabled for SLSEL0 default 1 D32 slave operations are enabled for SLSEL0 D3 D2 Address Space 0 0 A32...

Страница 140: ...s access and acquisition timings for slave transfers and slave block transfers for SLSEL0 in addition to data acquisition timing for master block transfers with local DMA This register is initialized...

Страница 141: ...uent cycle of a master block transfer with local DMA MBAT1 The delays are programmed in multiples of the 64 MHz clock period according to the following table D7 D6 D5 D4 Timing Delay 0 0 0 0 0 ns defa...

Страница 142: ...L0 SBAT0 rst cycle of a master block transfer with local DMA MBAT0 The delays are programmed in multiples of the 64 MHz clock period according to the following table D3 D2 D1 D0 Timing Delay 0 0 0 0 0...

Страница 143: ...remain clear Slave Select 1 Control Register 0 Master Write Post Enable bit D6 When this bit is set master write posting is enabled Write posting is not supported on the VMIVME 7487A therefore bit 6 s...

Страница 144: ...ster block transfers When performing BLT transfers bit 1 must always be set and bit 0 must be clear for accelerated local bus transfers D4 D32 Enable Bit Function 0 D32 slave operations are disabled f...

Страница 145: ...ve block transfers for SLSEL1 This register is initialized to a value of 00 upon powerup or hard reset Slave Select 1 Control Register 1 Timing Field 1 D7 D4 This bit eld establishes the following dat...

Страница 146: ...he following table D7 D6 D5 D4 Timing Delay 0 0 0 0 0 ns default 0 0 0 1 31 2500 ns 0 0 1 0 39 0625 ns 0 0 1 1 46 8750 ns 0 1 0 0 54 6875 ns 0 1 0 1 62 5000 ns 0 1 1 0 70 3125 ns 0 1 1 1 78 1250 ns 1...

Страница 147: ...ave block transfer for SLSEL1 SBAT0 The delays are programmed in multiples of the 64 MHz clock period according to the following table D3 D2 D1 D0 Timing Delay 0 0 0 0 0 ns default 0 0 0 1 31 2500 ns...

Страница 148: ...eld D5 D0 The burst length for block transfers with local DMA are con gured in this bit eld The value indicates the number of cycles per block transfer not the number of bytes A value of 0 in this bit...

Страница 149: ...t module based DMA transfers this bit must always remain clear When this bit is set module based DMA transfers are enabled Block Transfer Control Register Block Transfer with DMA bit D6 When this bit...

Страница 150: ...es the direction of a block transfer with local DMA MOVEM data direction determined by the R W signal When set VMEbus block reads occur When clear VMEbus block writes occur Block Transfer Control Regi...

Страница 151: ...D32 and D64 block transfers are supported If bit 0 of BTLR0 is set the block transfer length is ignored and only one burst is performed These registers are initialized to a value of 00 upon powerup or...

Страница 152: ...ple processors on the VMEbus Unlike the other VIC registers and System Registers most of these registers are available to both the local processor as well as all other VMEbus controllers Using these r...

Страница 153: ...et This is the only Interprocessor Communications Register that is not available to other VMEbus masters it is a local only register Interprocessor Communications Switch Register ICGS Switches bit fie...

Страница 154: ...ort I O offset address is 0B responding to both privileged and nonprivileged accesses This register provides the VIC or VIC64 version revision number Reset Halt Status Register The Reset Halt Status R...

Страница 155: ...gister ICR7 is a read write byte register at VIC offset I O address 47F Its VMEbus slave Short I O offset address is 0F responding to both privileged and nonprivileged accesses This register provides...

Страница 156: ...the slot 1 controller since an active SYSFAIL line may prevent the controller from performing its normal functions NOTE THE VMIVME 7487A ACTIVATES THE VMEbus SYSFAIL SIGNAL UPON POWERUP OR RESET IT IS...

Страница 157: ...slave register map These registers are slave only and not addressable in the local processor s I O space although they are available to the local processor through the VMEbus just as any VMEbus resour...

Страница 158: ...sociated function For example any write to address 21 sets the ICMS0 switch causing an interrupt on all masters that have not masked their ICMS0 switch Set Clear ICMS Switch Registers Slave Only ICMS0...

Страница 159: ...eir proper connector location Connector pins are clean and free from contamination No components of adjacent boards are disturbed when inserting or removing the board from the chassis Quality of cable...

Страница 160: ...MAINTENANCE 500 107487 000 M 2 VMIVME 7489 PRODUCT MANUAL...

Страница 161: ...NNECTOR PINOUT A 11 SECTION 10 VMEbus CONNECTOR PINOUT A 12 SECTION 1 INTRODUCTION The VMIVME 7487A PC AT Compatible VMEbus Controller has several connectors for its many I O ports Figure A 1 on page...

Страница 162: ...A Connector Locations J7 J6 Keyboard Port Parallel Port LPT1 IDE Hard Drive Port Floppy Drive Port P1 P2 J9 J8 PC 104 Bus J2 PC 104 Bus J3 PC 104 Expansion Site VMIVME 7487A COM1 Port RS 232 COM2 Port...

Страница 163: ...net option a D15 female connector provides the Ethernet AUI interface The pinout diagram for the Ethernet connector is shown in Figure A 2 Figure A 2 Ethernet Connector Pinout 8 9 15 1 ETHERNET CONNEC...

Страница 164: ...on some controllers 3 Ground 4 Reserved 5 Ground 6 From Controller Drive Density 1 not connected on some controllers 7 Ground 8 From Drive Index 9 Ground 10 From Controller Motor Enable A 11 Ground 1...

Страница 165: ...ional Data 10 9 In Out Bidirectional Data 04 10 In Out Bidirectional Data 11 11 In Out Bidirectional Data 03 12 In Out Bidirectional Data 12 13 In Out Bidirectional Data 02 14 In Out Bidirectional Dat...

Страница 166: ...a larger PC AT style connector to the VMIVME 7487A The PC AT style connector pinout is shown in Figure A 6 Figure A 5 PS 2 Keyboard Connector Pinout Figure A 6 PC AT Keyboard Connector Pinout 1 2 3 4...

Страница 167: ...able A 1 Figure A 7 PC 104 Connector Diagram Table A 1 PC 104 Connector Pinout PIN J1 ROW A J1 ROW B J2 ROW C J2 ROW D 0 0 V 0 V 1 IOCHCHK 0 V SBHE MEMCS16 2 SD7 RESETDRV LA23 IOCS16 3 SD6 5 V LA22 IR...

Страница 168: ...87A PRODUCT MANUAL 20 SA11 SYSCLK 21 SA10 IRQ7 22 SA9 IRQ6 23 SA8 IRQ5 24 SA7 IRQ4 25 SA6 IRQ3 26 SA5 DACK2 27 SA4 TC 28 SA3 BALE 29 SA2 5 V 30 SA1 OSC 31 SA0 0 V 32 0 V 0 V Table A 1 PC 104 Connector...

Страница 169: ...D0 3 In Out Bidirectional Data D1 4 In Out Bidirectional Data D2 5 In Out Bidirectional Data D3 6 In Out Bidirectional Data D4 7 In Out Bidirectional Data D5 8 In Out Bidirectional Data D6 9 In Out Bi...

Страница 170: ...DCD signal or the RI signal depending upon a jumper selection see Chapter 2 for complete board jumper information Figure A 9 Serial Connector Pinouts 5 9 6 1 SERIAL COM PORT CONNECTORS D9 PIN RJ45 PI...

Страница 171: ...sity D15 VGA connector Figure A 10 shows the pinout Figure A 10 Video Connector Pinout 5 12 6 1 VIDEO CONNECTOR PIN DIRECTION FUNCTION 1 Out Red 2 Out Green 3 Out Blue 4 Reserved 5 Ground 6 Ground 7 G...

Страница 172: ...igure A 11 VMEbus Connector Diagram Table A 2 VMEbus Connector Pinout PIN NUMBER P1 ROW A SIGNAL P1 ROW B SIGNAL P1 ROW C SIGNAL P2 ROW B SIGNAL 1 D00 BBSY D08 5 V 2 D01 BCLR D09 GND 3 D02 ACFAIL D10...

Страница 173: ...T A16 GND 23 AM4 GND A15 D24 24 A07 IRQ7 A14 D25 25 A06 IRQ6 A13 D26 26 A05 IRQ5 A12 D27 27 A04 IRQ4 A11 D28 28 A03 IRQ3 A10 D29 29 A02 IRQ2 A09 D30 30 A01 IRQ1 A08 D31 31 12 V 5 V STDBY 12 V GND 32 5...

Страница 174: ...APPENDIX A CONNECTOR PINOUTS 500 107489 000 A 14 VMIVME 7487A PRODUCT MANUAL...

Страница 175: ...r by means of a standard Ethernet AUI port on the controller s front panel A customer supplied AUI adapter connects to the Ethernet AUI port to provide the nal interface to the physical network which...

Страница 176: ...s DP83905 AT LANTIC VLSI chip This device is software compatible with Novell s NE2000 standard Any software that can be con gured to support an J7 J6 Keyboard Port Parallel Port LPT1 IDE Hard Drive P...

Страница 177: ...ociated Ethernet Mezzanine Option diskette This diskette contains the NIC Inspector and ATLES programs provided with the permission of National Semiconductor Corporation The NIC Inspector is a DOS pro...

Страница 178: ...anine ATLES is also a DOS program that provides diagnostic capabilities as well as the ability to make changes to the Ethernet Mezzanine settings These changes are stored into the small nonvolatile EE...

Страница 179: ...ed Boot EPROM resides in the U1 socket and is enabled the Ethernet Mezzanine also occupies up to 32 Kbytes in ISA memory space at a user selected address The ATLES program allows writing to the EEPROM...

Страница 180: ...ESS CONFLICTING WITH THE VGA AREA This produces a nonrecoverable FATAL error Table B 1 Boot EPROM Address Selection EPROM SIZE ADDRESS BOOT EPROM LOCATION none Factory Default no EPROM installed 8 o r...

Страница 181: ...with the 2 Mbyte Flash Memory Mezzanine option The Flash Memory Mezzanine allows the user to con gure the VMIVME 7487A as a diskless VMEbus master running software stored in the ash memory The Flash...

Страница 182: ...izontal jumper is located on the side of the Flash Memory Mezzanine as shown in Figure C 1 Figure C 1 Flash Mezzanine Jumper Location J7 J6 Keyboard Port Parallel Port LPT1 IDE Hard Drive Port Floppy...

Страница 183: ...ot the VMIVME 7487A 7 Observe DOS boot up The Flash BIOS should print out the following message during boot FLASH BIOS V1 0 C VMIC 1994 SECTION 3 COPYING FILES TO FLASH MEMORY 1 Prepare the Flash Memo...

Страница 184: ...rm whatever actions are necessary in the BIOS Setup program to disable oppy drive B and hard drive C Also ensure the system boot sequence searches drive A before drive C 5 If the VMIVME 7487A is to be...

Страница 185: ...the Flash Memory Mezzanine are zero wait state The Flash Memory Mezzanine bulk nonvolatile storage is I O mapped using an address pointer and a bidirectional data port The registers have the following...

Страница 186: ...ollowing publications by Intel or AMD for 28F020 programming algorithm information 1994 Flash Memory Volume I Intel Corporation Intel Literature Sales Department P O Box 7641 Mt Prospect IL 60056 7641...

Страница 187: ...UCTION This chapter describes how to use the PhoenixBIOS setup program and explains each con guration setting The menus displayed throughout this manual represent a typical system The actual menus dis...

Страница 188: ...rol of key click Last Boot Failed Mode NumLock control during bootup Automatic configuration of IDE fixed disks SECTION 3 QUICK SETUP If you are already familiar with BIOS setup programs this section...

Страница 189: ...hard disk select the IDE Adapter 0 Master sub menu and press Enter The IDE Adapter 0 Master sub menu displays F1 Help ESC Exit Select Item Select Menu ChangeValues Enter Select Sub Menu F9 Setup Def a...

Страница 190: ...and press Enter The BIOS automatically detects parameters for the hard drive 11 Check the parameters listed in the IDE Adapter 0 Slave sub menu and make necessary changes if the disk was not properly...

Страница 191: ...nixBIOS setup program consists of two menus the Main Menu and Exit Menu The Main Menu contains items and sub menus to configure standard system components such as the time and date floppy hard disk dr...

Страница 192: ...e eld enclosed by brackets where you can either key in the new values or use the keys 4 Arrows indicate sub menus Move to the sub menu and press Enter to access advanced settings 5 The Help Window pro...

Страница 193: ...h is enclosed by brackets 3 To change values use the keys and press Enter when done NOTE THE DEFAULT VALUE FOR F9 AND F10 IS ALWAYS N TO EXECUTE THESE ITEMS PRESS Enter TO CONTINUE Table D 1 PhoenixBI...

Страница 194: ...enus press Esc Main Menu items are described below along with the available values Sub menus are described in the following sections NOTE FACTORY DEFAULT SETTINGS FOR MENU ITEMS ARE DENOTED BY AN ASTE...

Страница 195: ...alled used for diskless workstations Video System Sets the type of video monitor The following settings provide compatibility to any standard video monitor Monochrome EGA VGA Color 80x25 Large Disk Mo...

Страница 196: ...er Figure D 4 below shows the IDE Adapter 0 Master sub menu Figure D 4 PhoenixBIOS IDE Adapter Master Sub menu The menu items available in both sub menus are described below Autotype Fixed Disk Automa...

Страница 197: ...ser user de ned disk parameters Set all disk parameters CAUTION Incorrect settings can cause your system to malfunction If you are not sure of the disk parameters use the Autotype Fixed disk menu item...

Страница 198: ...ad Sectors Wrt Pre 1 306 4 17 Should always be set to None 2 615 4 17 3 615 6 17 4 940 4 17 5 940 6 17 6 615 4 17 7 462 8 17 8 733 5 17 9 900 15 17 10 820 3 17 11 855 5 17 12 855 7 17 13 306 8 17 14 7...

Страница 199: ...per track 1 to 64 Write Precomp Sets the number of the cylinder at which to change the write timing 1 2048 None should always be selected for IDE hard disks 26 614 4 17 27 820 6 17 28 977 5 17 29 1218...

Страница 200: ...n Table D 5 on page D 14 Figure D 5 PhoenixBIOS Memory Cache Sub menu The items contained in this sub menu are described along with their available options NOTE THE FACTORY DEFAULT SETTINGS FOR MENU I...

Страница 201: ...nto external cache Disabled turns off the external cache NOTE IF CACHE ITEMS ARE DISABLED THE SPEED PERFORMANCE OF YOUR SYSTEM WILL BE DRASTICALLY REDUCED Cache Shadow Region Controls the cache shadow...

Страница 202: ...The factory default is 0 Kbytes Region 1 size Multiples of 16 de nes the size of non cacheable Region 1 in Kbytes The default setting is 0 Kbytes Disabled makes this region available for cache MEMORY...

Страница 203: ...ERISK System Shadow Permanently enabled Video Shadow Shadows video BIOS Enabled Disabled Shadow Memory Regions De nes the ROM shadow regions Main System Shado w Video shado w Shadow Memory Re gions C8...

Страница 204: ...FFF De nes the VMEbus access which should not be shadowed This setting should always be disabled Enabled Disabled BOOT OPTIONS SUB MENU The Boot Options sub menu contains items that enable you to con...

Страница 205: ...stalled system boots with a keyboard installed Uninstalled system boots without a keyboard Boot Sequence Sets the system s boot drive A then C system attempts to boot from floppy drive A then hard dri...

Страница 206: ...a Power On Self Test POST error occurs POST is a series of system diagnostic routines performed during system boot Enabled displays the SETUP prompt along with the appropriate error message Disabled...

Страница 207: ...hnologies Ltd CPU 66 MHz 486DX2 Coprocessor Installed System R OM FAB6 FFFF BIOS Date 01 28 95 System RAM 640Kb Extended RAM 15360Kb Shadow RAM 384Kb Cache RAM None COM Ports 03F8 02F8 LPT Ports 0378...

Страница 208: ...k on if it nds a numeric key pad Key click Controls audible key click Enabled Disabled Keyboard Auto Repeat Rate Controls the speed at which a keystroke is repeated per second The possible values for...

Страница 209: ...he setup program and reboots the system The new menu items stored in CMOS battery backed CMOS RAM are used Discard Changes Exit Exits the program without saving any menu settings At system boot up the...

Страница 210: ...types on the Main Menu Load Previous Values Resets all menu items to values previously set in CMOS Select this item and press Enter to reload the menu items Select Y at the con rmation prompt to cont...

Страница 211: ...set nnnn nnnn Extended RAM Passed Where nnnn is the amount of RAM in Kbytes successfully tested Failing Bits nnnn The hex number nnnn is a map of the bits at the RAM address in System Extended or Shad...

Страница 212: ...resume F2 to Setup Displayed after any recoverable error message Press F1 to start the boot process or F2 to enter the setup program and change any settings Press F2 to enter SETUP Optional message di...

Страница 213: ...am that changes data stored in CMOS Run the setup program and reconfigure the system either by getting the Default Values and or making your own selections System RAM Failed at offset nnnn System RAM...

Страница 214: ...APPENDIX D BASIC INPUT OUTPUT SYSTEM 500 107487 000 D 28 VMIVME 7487A PRODUCT MANUAL...

Страница 215: ...uipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentat...

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