PKP
VS1000 P
ROGRAMMER
’
S
G
UIDE
VSMPG
13.4
Overview of VS1000 Clocking
Below is a diagram showing the basic layout of the clock signal paths in VS1000:
2
1
0
2
1
0
1
0
1
0
Analog Block
XTALI
SCI_SYSTEM[15]
256
FREQCTLH[8]
Multiplier
FREQCTLH[7:4]
FREQCTLH[9]
4
CLKI
SCI_STATUS[15]
(should be
12..13 MHz
when playing)
To Core
Figure 8: VS1000 Clocking
With a 12.0000 megahertz crystal, the following core clock speeds are within limits:
Core Frequency Calculation
XTALIN=12.000 MHz
Register Values
Result
SCI_SYSTEM[15]
SCI_ST
A
TUS[15]
FREQCTLH[9]
FREQCTLH[8]
FREQCTLH[7:4]
Registers:
SCI_SYSTEM[15]
XTALI divide by 2
SCI_STATUS[15]
XTALI divide by 256
FREQCTLH[9]
Use PLL
FREQCTLH[8]
Divide PLL input clock by 2
FREQCTLH[7:4]
PLL rate control
1
1
0
0
0000
0.02344 MHz (23.438 kHz) (Lower CVDD possible)
0
1
0
0
0000
0.04688 MHz
1
0
0
0
0000
6 MHz
0
0
0
0
0000
12 MHz
0
0
1
1
0010
18 MHz
0
0
1
0
0001
24 MHz
0
0
1
1
0100
30 MHz
0
0
1
0
0010
36 MHz
0
0
1
1
0110
42 MHz
0
0
1
0
0011
48 MHz (required by USB, maximum used by ROM code)
0
0
1
1
1000
54 MHz
0
0
1
0
0100
60 MHz (Possible with high CVDD but not recommended)
Rev. 0.20
2011-10-04
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