PKP
VS1000 P
ROGRAMMER
’
S
G
UIDE
VSMPG
12.3
Conserving Power
Three main factors affect the power requirement of any CMOS device are clock fre-
quency, voltage, and leakage. Of these, clock frequency has the greatest effect to power
consumption.
The Clock frequency of VS1000 is controlled by
•
The XTALI input (crystal oscillator)
•
The System Controller
•
The PLL (Phase Locked Loop) Controller (Clock multiplier)
The System Controller’s role in clock control is providing two clock dividers between the
crystal oscillator output and the analog block and the PLL controller. First there is a
divide-by-2 block, which is controlled by SCISTF_SLOW_CLKMODE. After that there is
a divide-by-256 block, which is controlled by SCISYSF_CLKDIV.
The divide-by-2 block is normally used when there is a 24 MHz crystal connected to the
XTALI/XTALO pins (normally a 12 MHz crystal is used). Setting SCISTF_SLOW_CLK-
MODE affects all system frequencies, including the PLL, but it does not prohibit using
PLL.
It should be noted that the analog block requires 12 MHz from System Controller for
proper performance.
The divide-by-256 block is used to considerably cut down power consumption. This is
especially useful when some basic operation is needed (such as the capability to recover
from USB suspend or resume after low-power PAUSE mode) but battery life needs to
be extended.
The PLL must not be used when divide-by-256 is active. The PLL tries and fails to lock
to a frequency below PLL minimum. Switch off PLL (set 1 x clock multiplier) before
setting SCISYSF_CLKDIV.
If divide-by-256 is activated without first switching the analog drivers off, the DAC sigma-
delta modulator noise (which is part of normal sigma-delta operation) drops down to au-
dible frequencies, which is undesired. To overcome this, set SCISTF_ANADRV_PDOWN
before activating SCISYSF_CLKDIV. You should also write 0 to DAC_LEFT DAC_RIGHT
to further diminish digital noise and power consumption. Remember to restore the val-
ues before resuming playback.
If playback will resume directly after recovering from the power down state, it is not
recommended to set SCISTF_ANA_PDOWN since restoring the bias voltages of the
analog block can result in a power-up pop sound. If that is not relevant (such as in a
USB suspend condition,) SCISTF_ANA_PDOWN should be asserted to further mini-
mize power consumption. Also setting the AVDD, DVDD and CVDD to a lower level will
diminish power consumption.
Rev. 0.20
2011-10-04
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