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Chapter 4 Deployment CPU 313SC/DPM
Manual VIPA System 300S SPEED7
4-4 HB140E - CPU SC - RE_313-6CF03 - Rev. 07/45
Addressing
To provide specific addressing of the integrated in-/output periphery and
the installed peripheral modules, certain addresses must be allocated in
the CPU.
At the start-up of the CPU, this assigns automatically peripheral addresses
for digital in-/output modules starting with 0 and ascending depending on the
slot location.
If no hardware project engineering is available, the CPU stores at the
addressing analog modules to even addresses starting with 256.
The integrated in-/output periphery is also allocated to the address area of
the CPU. More may be found at "Address assignment".
The CPU provides an I/O area (address 0 ... 8191) and a process image of
the in- and outputs (each address 0 ... 127).
The process image stores the signal states of the lower address (0 ... 127)
additionally in a separate memory area.
The process image this divided into two parts:
•
process image to the inputs (PII)
•
process image to the outputs (PIQ)
I/O area
0
.
.
.
.
127
.
.
.
.
8191
Process image
0
.
.
.
127
0
.
.
.
127
Inputs
PII
Outputs
PIQ
Digital modules
Analog modules
The process image is updated automatically when a cycle has been
completed.
In the hardware configurator from Siemens you may parameterize maximum
up to 8 modules per row. At deployment of the SC CPU you may control up
to 31 modules at the bus.
For the project engineering of more than 8 modules you may use virtual
line interface connections. For this you set in the hardware configurator the
module IM 360 from the hardware catalog to slot 3 of your 1
st
profile rail.
Now you may extend your system with up to 3 profile rails by starting each
with an IM 361 from Siemens at slot 3.
Overview
Addressing
Backplane bus
I/O devices
Max. number of
pluggable
modules