UG:014
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Page 7
Schematics
Figure 3a.
Schematic - Full Chip VTM
evaluation board
12
06
C
12
12
06
C
16
12
06
C
13
12
06
C
17
12
06
C
14
12
06
C
18
12
06
C
15
12
06
C
19
T
P1
1
T
P1
0
T
P2
0
T
P1
7
T
P2
2
T
P2
1
T
P1
2
12
10
C
21
12
10
C
22
12
10
C
20
12
06
R
16
12
06
R
15
12
06
R
13
J1
3
J1
0
J1
6
T
P2
4
T
P2
5
T
P2
6
J1
2
V
C
T
M
P
C
P
C
T
M
V
C
-I
N
H
12
H
13
P
C
T
M
+
O
U
T
-O
U
T
-I
N
+
O
U
T
-O
U
T
H
23
H
24
V
C
H
11
H
10
CI
N
12
06
R
18
T
P1
4
T
P1
5
-S
E
NS
E
+
SENS
E
12
06
R
17
06
03
R
11
06
03
R
10
H
18
H
19
T
P1
9
T
P1
8
06
03
R
14
06
03
C
11
T
M
T
M
_
F
-I
N
12
06
R
12
06
03
C
10
T
P1
6
H
14
H
15
N
O
G
N
D
H
S1
0
T
P1
3
H
16
+I
N
-I
N
+O
U
T
-O
U
T
T
M
V
T
M
V
C
P
C
P
RI
M
A
R
Y
SE
C
O
N
D
A
R
Y
IS
O
LA
T
IO
N
B
O
U
N
D
R
Y
P
S1
0
V
T
M
_
OFF
_B
D
_V
IB
R
IC
K
25
12
R
19
H
25
H
26
1
2
3
4
5
6
7
8
9
10
J1
1
1
2
3
4
5
6
7
8
9
10
J1
4
FI
D
U
C
IA
L
F
ID
01
FI
D
U
C
IA
L
F
ID
02
H
21
H
20
H
22
H
17
K
EL
V
IN
WI
TH
D
IFF
E
RE
N
T
IA
L
R
O
U
T
IN
G
K
EL
V
IN
T
P2
9
T
P2
7
T
P2
3
T
P2
8
J1
5
-I
N
K
EL
V
IN
-
IN
K
EL
V
IN
-
IN
