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Chapter 2 Data Communications Testing
Selecting a BER pattern
Data Communications and Diphase Testing Manual
Page 18 21148872, Rev. 002 January 2016
Table 7 lists the available BER patterns for the instrument.
Table 7 BER patterns
Pattern Description Provides
Mark All ones Logic one (idle condition) data signal. Intended to test
transmission circuits for maximum ones condition.
NOTE: When you set up the instrument to transmit
the MARK pattern and to use an internal clock source
for the received data,
and the unit is not connected to
a circuit (or the connection is broken):
– The Pattern Sync LED illuminates.
– The Signal/Clk Present LED
illuminates.
– The ALL SUMMARY RESULTS OK
display appears.
This is because the unit obtains pattern sync with the
MARKs (idles) received by its internal Rx chip.
Space All zeros Logic zero data signal. Intended to test transmission
circuits for maximum zeroes condition.
1:1 10,10… Minimum stress on clock recovery circuits.
1:3 1000,1000… A 1 followed by three 0s.
1:4 10000,10000… A 1 followed by 4 0s.
1:7 10000000,10000000
… Maximum stress of the 12.5% ones density require-
ments for T1 circuits.
3:1 1110,1110… Three 1s followed by one 0 (1110) pattern.
7:1 11111110,11111110… Seven 1s followed by one 0 (11111110) pattern.
63 2
6
-1 Selects the 2
6
-1 Pseudorandom pattern, which gener-
ates a maximum of 5 sequential 0s and 6 sequential
1s. This pattern provides the lowest stress of any
pseudorandom pattern.
511 2
9
-1 2
9
-1 pseudorandom pattern with a maximum of 8
sequential zeros and 9 sequential ones. Simulates
live traffic on DDS circuits. Compatible with DDS
equipment. Recommended when testing below
9.6 Kbps.
2047 2
11
-1 2
11
-1 pseudorandom pattern with a maximum of 10
sequential zeros and 11 sequential ones. Simulates
live traffic on DDS circuits. Compatible with DDS
equipment. Used for testing data rates between 9.6
and 56 Kbps.
2047 Rev 2
11
-1 Reversed 2047 reversed.
2047 Rev-Inv 2
11
-1 Reversed and
Inverted
2047 reversed and inverted.