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EPM-32 Reference Manual
47
Special Registers
Special Control Register
SCR (READ/WRITE) 1D0h (or 1E0h via CMOS Setup)
D7
D6
D5
D4
D3
D2
D1
D0
PLED
Reserved
OVERTEMP
HDOGNMI
COMDIR
WDOG_STA
WDOG_NMI
WDOG_RST
Table 20: Special Control Register Bit Assignments
Bit
Mnemonic
Description
D7
PLED
Light Emitting Diode
— Controls the programmable LED on connector J4.
PLED = 0
Turns LED off
PLED = 1
Turns LED on
D6
Reserved
Reserved
— This bit has no function.
D5
OVERTEMP
Temperature Status
—
Indicates CPU temperature.
OVERTEMP = 0 CPU temperature is below value set in the CMOS setup
OVERTEMP = 1 CPU temperature is above value set in the CMOS setup
Note:
This bit is a read-only bit.
D4
HDOGNMI
Non-Maskable Interrupt Enable
— Controls the generation of NMIS whenever
the CPU temperature sensor detects an over-temperature condition.
HDOGNMI = 0
Disable
HDOGNMI = 1
Enable
D3
COMDIR
COM2 RS-485 Transmit Enable
— Enables the RS-485 transmitter.
COMDIR = 0
Receive
COMDIR = 1
Transmit
D2
WDOG_STA
WDOG STATUS
— Indicates if the watchdog timer has expired.
WDOG_STA = 0 Timer has not expired
WDOG_STA = 1 Timer has expired
Note:
Do not write to this bit.
D1
WDOG_NMI
Watchdog Non-Maskable Interrupt Enable
— Enables the generation of a NMI
when the watchdog timer expires.
WDOG_NMI = 0 Disables
WDOG_NMI = 1 Enables
D0
WDOG_RST
Watchdog Reset Enable
— Enables and disables the watchdog timer reset
circuit.
WDOG_RST = 0 Disables
WDOG_RST = 1 Enables
7
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