Interfaces and Connectors
Bengal (VL-EPMe-30) Reference Manual
45
SPI Registers
A set of control and data registers are available for SPI transactions. The following tables describe
the SPI control registers (SPICONTROL and SPISTATUS) and data registers (SPIDATA3-0).
SPICONTROL (READ/WRITE) C88h
D7
D6
D5
D4
D3
D2
D1
D0
CPOL
CPHA
SPILEN1
SPILEN0
MAN_SS
SS2
SS1
SS0
Table 25: SPI Control Register 1 Bit Assignments
Bit
Mnemonic
Description
D7
CPOL
SPI Clock Polarity
– Sets the SCLK idle state.
0 = SCLK idles low
1 = SCLK idles high
D6
CPHA
SPI Clock Phase
–
Sets the SCLK edge on which valid data will be read.
0 = Data read on rising edge
1 = Data read on falling edge
D5-D4
SPILEN(1:0)
SPI Frame Length
–
Sets the SPI frame length. This selection works in
manual and auto slave select modes.
SPILEN1
SPILEN0
Frame Length
0
0
1
1
0
1
0
1
8-bit
16-bit
24-bit
32-bit
D3
MAN_SS
SPI Manual Slave Select Mode
–
This bit determines whether the slave
select lines are controlled through the user software or are automatically
controlled by a write operation to SPIDATA3 (CADh). If MAN_SS = 0, then the
slave select operates automatically; if MAN_SS = 1, then the slave select line
is controlled manually through SPICONTROL bits SS2, SS1, and SS0.
0 = Automatic, default
1 = Manual
D2-D0
SS(2:0)
SPI Slave Select
– These bits determine which slave select will be asserted.
The SSx# pin on the baseboard will be directly controlled by these bits when
MAN_SS = 1.
ADIOMODE
= 0 (default mode)
SS2
SS1
SS0
Slave Select
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None, port disabled
SPX Slave Select 0, J28 pin-8
SPX Slave Select 1, J28 pin-9
SPX Slave Select 2, J28 pin-10
SPX Slave Select 3, J28 pin-11
Not supported
Not supported
Not supported
