ZOE-M8 series - Hardware integration manual
UBX-16030136 - R09
Design-in
Page 8 of 34
Production information
2.2
Interfaces
The ZOE-M8 GNSS SiPs provide UART, SPI and DDC (I2C-compatible) interfaces for communication
with a host CPU. Additionally, an SQI interface is available for connecting the ZOE-M8 GNSS SiPs with
an optional external flash memory.
The UART, SPI and DDC pins are supplied by VCC and operate at this voltage level.
Four dedicated pins can be configured as either 1 x UART and 1 x DDC or a single SPI interface
selectable by the D_SEL pin. Table 2 below provides the port mapping details.
Pin #
Pin D4 (D_SEL) = “high” (left open)
Pin D4 (D_SEL) = “Low” (connected to GND)
J5
UART TXD
SPI MISO
J4
UART RXD
SPI MOSI
B1
DDC SCL
SPI CLK
A2
DDC SDA
SPI CS_N
Table 2: Communication interfaces overview
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It is not possible to use the SPI interface simultaneously with the DDC or UART interface.
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For debugging purposes, it is recommended to have a second interface, for example, DDC available
that is independent from the application and accessible via test-points.
For each interface, define a dedicated pin to indicate that data is ready to be transmitted. The TXD
Ready signal indicates that the receiver has data to transmit. Each TXD Ready signal is associated
with a particular interface and cannot be shared. A listener can wait on the TXD Ready signal instead
of polling the DDC or SPI interfaces. The UBX-CFG-PRT message lets you configure the polarity and
the number of bytes in the buffer before the TXD Ready signal goes active. The TX Ready signal can
be mapped, for example, to UART TX. The TXD Ready function is disabled by default.
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The TXD Ready functionality can be enabled and configured by using suitable AT commands sent
to the u-blox cellular module in question that supports the feature. For more information, see the
GPS Implementation and Aiding Features in u-blox wireless modules [5].
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The TXD Ready feature is supported on several u-blox cellular module products.
2.2.1
UART interface
A UART interface is available for serial communication to a host CPU. The UART interface supports
configurable data rates with the default at 9600 baud. Signal levels are related to the VCC supply
voltage. An interface based on RS232 standard levels (+/- 7 V) can be realized using level shifter ICs
such as the Maxim MAX3232.
Hardware handshake signals and synchronous operation are not supported.
A signal change on the UART RXD pin can also be used to wake up the receiver in power save mode
(see the u-blox 8 / u-blox M8 Receiver Description including Protocol Specification
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Designs must allow access to the UART and the SAFEBOOT_N pin for future service, updates, and
reconfiguration.
2.2.2
Display data channel (DDC) interface
An I2C-compatible display data channel (DDC) interface is available for serial communication with a
host CPU.
