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EVK-NORA-W1 - User guide 

UBX-22002764 - R02 

Hardware description  

Page 15 of 22 

C1-Public  

 

 

 

3.9

 

External JTAG debug interface 

External target hardware can be attached to the J20 header connector for firmware programming 
and debug. J20 is implemented with a 2x5 header with 1.27 mm pitch. 

Figure 13

 shows the physical 

layout of connector. 

 

Figure 14: J20 physical layout 

 

Figure 15

 shows a schematic diagram of the JTAG debug interface.  

 
 

  

 

Figure 15: External JTAG debug interface

 

Содержание NORA-W10 Series

Страница 1: ...bstract The document describes how to set up and use the EVK NORA W101 and EVK NORA W106 evaluation kits for prototyping NORA W10 open CPU multiradio modules To obtain the different options for debugg...

Страница 2: ...ct specification This document applies to the following products Product name Document status EVK NORA W101 Objective specification EVK NORA W106 Objective specification For information about the hard...

Страница 3: ...Setting up the evaluation board 6 3 Hardware description 7 3 1 Overview 7 3 2 Power 7 3 2 1 Powering the board 8 3 3 Reset 9 3 4 Buttons 10 3 5 LEDs 11 3 6 Serial communication 12 3 7 32 768 kHz low f...

Страница 4: ...existing Arduino shields Current sense resistors allow for measuring current into the module and into the shield This guide provides setup instructions for starting development and describes the hard...

Страница 5: ...es 1 2 1 EVK NORA W101 EVK NORA W10 evaluation board with NORA W101 module USB C to USB A adapter cable 2 4 GHz U FL antenna 1 2 2 EVK NORA W106 EVK NORA W10 evaluation board with NORA W106 module equ...

Страница 6: ...g system installs the correct COM port drivers automatically The drivers need to be installed only when you connect the unit to a new computer for the first time For more information about the COM por...

Страница 7: ...r sources are separated using a Schottky diode D1 D3 MBR120VLSFT3G The diode prevents reverse voltage to any of the other supplies which means that the power sources can be connected simultaneously Se...

Страница 8: ...e board Set the power switch SW6 ON to extend the VBUS supply to the 3 3 V LDO regulator and power up the board The LDO regulator powers the 3V3 VDD and VDD IO power rails The green LED D1 is lit when...

Страница 9: ...eset in bootloader mode See also Figure 5 Figure 5 EVK schematic reset and boot buttons UART DTR and UART RTS can be used to initiate BOOT and nRESET as an alternative to using the buttons SW2 and SW5...

Страница 10: ...nd when pressed The functionality of these buttons is controlled by the system software through the GPIO interface The buttons and the associated GPIO signals are shown in Figure 7 The BOOTn button is...

Страница 11: ...oard when lit green UART0 status D4 D9 Indicates UART0 signal status under GPIO control as shown in Figure 9 System status RGB1 Powered by 3V3 and turned on by pulling the associated GPIO low Disconne...

Страница 12: ...ation The evaluation board allows for easy serial communication with the NORA W10 module and a connected computer through a single FTDI USB to UART IC that provides one COM port The COM port is connec...

Страница 13: ...rawing 1 port default 3 7 32 768 kHz low frequency clock The evaluation board has a 32 768 kHz crystal connected to the NORA W10 module to allow use of the external crystal oscillator option to source...

Страница 14: ...f the 2 54 mm pitch 3 pin headers has two pins connected across a 1 current sense resistors RMOD and RIO respectively with the third connected to GND The module VDD and VDD IO supplies are sourced thr...

Страница 15: ...get hardware can be attached to the J20 header connector for firmware programming and debug J20 is implemented with a 2x5 header with 1 27 mm pitch Figure 13 shows the physical layout of connector Fig...

Страница 16: ...resistor R70 or R71 to select the preferred choice of power supply to the SPI flash memory chip Figure 16 Quad PSRAM EVK schematic and EVK board view Table 6 shows the respective SPI functions for co...

Страница 17: ...omponents from the GPIO nets and subsequently eliminate interference generated by any external circuits attached to the I O sockets female The physical location of the jumpers is shown in Figure 17 Fi...

Страница 18: ...J2 connector GPIO15 J21 Solder bridge Connected to 32KHz clock XT 32k n Cut and close to J2 connector GPIO16 Table 7 Solder bridge jumpers overview 3 12 Header pin out Figure 14 shows the 2 54 mm pit...

Страница 19: ...O12 G2 GPIO ADC2 CH1 3 GPIO13 A6 GPIO ADC2 CH2 4 GPIO5 J8 GPIO ADC1 CH4 5 GPIO15 C6 GPIO ADC2 CH4 XTAL 32K P 6 GPIO16 B6 GPIO ADC2 CH5 XTAL 32K N Table 9 Header J2 analog IO Pin Pin name NORA W1 pin F...

Страница 20: ...8 E3 SPICLK_N 7 GPIO18 B4 SDA 8 GPIO17 A3 SCL Table 12 Header J5 digital IO Pin Pin name NORA W1 pin Function 1 3V3 Supply 2 JTAG TMS H2 GPIO42 if J15 is changed 3 GND Ground 4 JTAG TCK J2 GPIO 39 if...

Страница 21: ...pose Input Output LDO Low Drop Out voltage regulator LE Low Energy LED Light Emitting Diode LF Low Frequency LiPo Lithium Polymer battery NCS nRF Connect SDK NFC Near Field Communications QSPI Quad Se...

Страница 22: ...sion Date Name Comments R01 2022 04 29 ovik hekf Initial release for EVK NORA W1 PT2 R02 2022 07 22 hekf Editorial changes in all chapters Added hardware Overview and updated Setting up the evaluation...

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