NEO-D9S - Integration manual
of a valid message. If the message data is ready for transmission, the successive reads of register
0xFF will deliver the waiting message data.
Do not use registers 0x00 to 0xFC. They are reserved for future use and they do not
currently provide any meaningful data.
Figure 5: I2C register layout
3.2.2.2 Read access types
There are two I2C read transfer forms:
• The "random access" form: includes a slave register address and allows any register to be read.
• The "current address" form: omits the register address.
shows the format of the first one, the "random access" form of the request. Following the
start condition from the master, the 7-bit device address and the RW bit (which is a logic low for
write access) are clocked onto the bus by the master transmitter. The receiver answers with an
acknowledge (logic low) to indicate that it recognizes the address.
Next, the 8-bit address of the register to be read must be written to the bus. Following the receiver's
acknowledgment, the master again triggers a start condition and writes the device address, but this
time the RW bit is a logic high to initiate the read access. Now, the master can read 1 to N bytes
from the receiver, generating a not-acknowledge and a stop condition after the last byte being read.
UBX-19026111 - R07
3 Receiver functionality
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