TOBY-L1 and MPCI-L1 series - System Integration Manual
UBX-13001482 - R04
Advance Information
Design-in
Page 74 of 90
2.16
Design-in checklist
This section provides a design-in checklist.
2.16.1
Schematic checklist
The following are the most important points for a simple schematic check:
DC supply must provide a nominal voltage at
VCC / 3.3aux
pin within the operating range limits.
DC supply must be capable of support with adequate margin the highest averaged current consumption
value in connected-mode conditions specified in
TOBY-L1 series Data Sheet
[1] and
MPCI-L1 series Data
Sheet
VCC / 3.3aux
supply should be clean, with very low ripple/noise: provide the suggested bypass
capacitors, in particular if the application device integrates an internal antenna.
For TOBY-L1 series modules, do not leave
PWR_ON
floating: fix properly the level, e.g. adding a proper
pull-up resistor to
V_BCKP
.
For TOBY-L1 series modules, do not apply loads which might exceed the limit for maximum available
current from
V_INT
supply.
Check that voltage level of any connected pin does not exceed the related operating range.
Check
USB_D+
/
USB_D-
signal lines as well as very low capacitance ESD protections if accessible.
Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications.
Insert the suggested capacitors on each SIM signal and low capacitance ESD protections if accessible.
For TOBY-L1 series modules, provide accessible test points directly connected to the following pins:
V_INT
,
PWR_ON
,
RESET_N
and to
RSVD
pins 16, 17, 49 for diagnostic purpose.
Provide proper precautions for ESD immunity as required on the application board.
All unused pins can be left unconnected except the
PWR_ON
pin (its level must be properly fixed, e.g.
adding a 100 k
Ω
pull-up to
V_BCKP
).
2.16.2
Layout checklist
The following are the most important points for a simple layout check:
Check 50
Ω
nominal characteristic impedance of the RF transmission line connected to the
ANT1
and
the
ANT2
pads (antenna RF interfaces).
Ensure no coupling occurs between the RF interface and noisy or sensitive signals (primarily USB signals,
digital input/output signals, SIM signals, high-speed digital lines such as address and data lines).
VCC
/
3.3Vaux
line should be wide and short. VCC regulator should be as close as possible to the
module.
Route
VCC
/
3.3Vaux
supply line away from sensitive analog signals.
Ensure proper grounding.
Optimize placement for minimum length of RF line and closer path from DC source for
VCC
/
3.3Vaux
.
Keep routing short and minimize parasitic capacitance on the SIM lines to preserve signal integrity.
USB_D+
/
USB_D-
traces should meet the characteristic impedance requirement (90
Ω
differential and
30
Ω
common mode) and should not be routed close to any RF traces.
