MIA-M10Q - Integration manual
Figure 6: I2C register layout
2.3.2.2 Read access types
The host can choose one of the following two modes:
• Random read access: the master first reads the number of available bytes at the 0xFD and
0xFE before accessing the data at 0xFF.
• Current address read access: the master directly reads the data at the register 0xFF, without
knowing first if there is any data waiting. If there is no data, the read result is a 0xFF byte value.
This mode basically skips the first step of the "random read access", as it does not address to
any particular register.
shows the format of the "random access" form of the request.
Following the start condition from the master, the 7-bit device address and the RW bit (which is a
logic low for write access) are clocked onto the bus by the master transmitter. The receiver answers
with an acknowledge (logic low) to indicate that it recognizes the address.
Next, the 8-bit address of the register to be read must be written to the bus (0xFD for u-blox
receivers). Following the receiver's acknowledgment, the master again triggers a start condition and
writes the device address, but this time the RW bit is a logic high to initiate the read access. Now,
the master can read 1 to N bytes from the receiver. The receiver will first deliver the byte value at
0xFD, followed by the value at 0xFE. At this point the master knows the number of bytes waiting at
the 0xFF register, and by acknowledging again, the data stream follows. The data transfer will stop
once the master emits a not-acknowledge response or a stop condition is triggered after the last
byte has been read.
UBX-21028173 - R01
2 Receiver functionality
Page 23 of 89
C1-Public
