LISA-U2 series - System Integration Manual
UBX-13001118 - R19
Early Production Information
System description
Page 79 of 175
1.9.4.1
IPC communication protocol overview
The module runs as an SPI slave, i.e. it accepts AT commands on its SPI interface without specific configuration.
The SPI-device shall look for all upper-SW-layers like any other serial device. This means that LISA-U2 modules
emulate all serial logical lines: the transmission and the reception of the data are similar to an asynchronous
device.
Two additional signals (
SPI_MRDY
and
SPI_SRDY
) are added to the SPI lines to communicate the state of
readiness of the two processors: they are used as handshake signals to implement the data flow.
The function of the
SPI_MRDY
and
SPI_SRDY
signals is twofold:
For transmitting data the signal indicates to the data receiver that data is available to be transmitted
For receiving data the signal indicates to the transmitter that the receiver is ready to receive data
Due to this setup it is possible to use the control signals as interrupt lines waking up the receiving part when
data is available for transfer. When the handshaking has taken place, the transfer occurs just as if it were a
standard SPI interface without chip select functionality (i.e. one master - one slave setup).
SPI_MRDY
is used by the application processor (i.e. the master) to indicate to the module baseband processor
(i.e. the slave) that it is ready to transmit or receive (IPC master ready signal), and can also be used by the
application processor to wake up the module baseband processor if it is in idle-mode.
SPI_SRDY
line is used by the module baseband processor (i.e. the slave) to indicate to the application processor
(i.e. the master) that it is ready to transmit or receive (IPC slave ready signal), and can also be used by the module
baseband processor to wake up the application processor if it is in hibernation.
SPI_MRDY
SPI_SRDY
DATA_EXCHANGE
SPI_MOSI
SPI_MISO
Header
Data
SPI_SCLK
Figure 41: IPC Data Flow: SPI_MRDY and SPI_SRDY line usage combined with the SPI protocol
For the correct implementation of the SPI protocol, the frame size is known by both sides before a packet
transfer of each packet. The frame is composed by a header with fixed size (always 4 bytes) and a payload with
variable length (must be a multiple of 4 bytes).
The same amount of data is exchanged in both directions simultaneously. Both sides set their readiness lines
(
SPI_MRDY
/
SPI_SRDY
) independently when they are ready to transfer data. For the correct transmission of the
data the other side must wait for the activating interrupt to allow the transfer of the other side.
The master starts the clock shortly after
SPI_MRDY
and
SPI_SRDY
are set to active. The number of clock
periods sent by the master is exactly that one of the frame-size to be transferred. The
SPI_SRDY
line will be set
low after the master sets the clock line to idle state. The
SPI_MRDY
line is also set inactive after the clock line is
set idle, but in case of a big transfer containing multiple packets, the
SPI_MRDY
line stays active.
1.9.4.2
IPC communication and power saving
If power saving is enabled by AT command (AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3), the LISA-U2 module
automatically enters idle-mode whenever possible, if the master indicates that it is not ready to transmit or
receive by the
SPI_MRDY
signal, or if the LISA-U2 series module itself does not transfer data.
