LISA-U series - System Integration Manual
UBX-13001118 - R17
Advance information
Design-In
Page 149 of 190
External Antenna Enclosure
Application Board
LISA-U2x0-xxS
ANT
Radiating
Element
Zo = 50 Ohm
Coaxial Antenna Cable
Antenna Port
Enclosure Port
C
L
Figure 82: Antenna port ESD immunity protection application circuit for LISA-U2 series modules
Reference
Description
Part Number - Manufacturer
C
15 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H150JA01 - Murata
L
39 nH Multilayer Chip Inductor L0G 0402 5%
LQG15HN39NJ02 - Murata
Table 56: Example of components for Antenna port ESD immunity protection application circuit for LISA-U2 series modules
With LISA-U230 modules, the
ANT_DIV
pin provides ESD immunity up to +4 kV / -4 kV for direct Contact
Discharge and up to +8 kV / -8 kV for Air Discharge: no further precaution to ESD immunity test is needed, as
implemented in the EMC / ESD approved reference design of LISA-U230 modules.
RESET_N pin
The following precautions are suggested for the
RESET_N
line of LISA-U modules, depending on the application
board handling, to satisfy ESD immunity test requirements:
A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01) must be mounted on the line termination
connected to the
RESET_N
pin to avoid a module reset caused by an electrostatic discharge applied to the
application board enclosure
A proper series chip ferrite bead noise/EMI suppression filter (e.g. Murata BLM15HD182SN1) must be added
on the line connected to the
RESET_N
pin to avoid a module reset caused by an electrostatic discharge
applied to the application board enclosure
An additional 220 nF bypass capacitor (e.g. Murata GRM155R60J224KE01) must be mounted as close as
possible to the
RESET_N
pin of LISA-U2 series modules to avoid a module reset caused by an electrostatic
discharge applied to the application board enclosure
It is recommended to keep the connection line to
RESET_N
as short as possible
Maximum ESD sensitivity rating of the
RESET_N
pin is 1 kV (Human Body Model according to JESD22-A114F).
Higher protection level could be required if the
RESET_N
pin is externally accessible on the application board.
The following precautions are suggested to achieve higher protection level:
A general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS
CT0402S14AHSG varistor) should be mounted on the
RESET_N
line, close to accessible point