AMY-6M - Hardware Integration Manual
UBX-17021971 – R07
Appendix
Page 50 of 57
C
Interface Backgrounder
C.1
DDC Interface
Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus.
These lines are connected to all devices on the DDC. SCL is used to synchronize data transfers and SDA is the
data line. Both SCL and SDA lines are "open drain" drivers. This means that DDC devices can only drive them
low or leave them open. The
pull-up resistor (Rp) pulls the line up to V
DD
if no DDC device is pulling it down to
GND. If the pull-up resistors are missing, the SCL and SDA lines are undefined and the DDC bus will not work.
For most DDC systems the low and high input voltage level thresholds of SDA and SCL depend on V
DD
. See the
AMY-6M Data Sheet
[1] for the applicable voltage levels.
D D C D e v ic e A
D D C D e v ic e B
V
D D
S DA
S CL
GND
Rp
Rp
S DA in
S DA out
S CL in
S DA out
S DA in
S DA out
S CL in
S DA out
Figure 37: A simple DDC connection
The signal shape and the maximum rate in which data can be transferred over SDA and SCL is limited by the
values of Rp and the wire and I/O capacitance (Cp). Long wires and a large number of devices on the bus
increase Cp, therefore DDC connections should always be as short as possible. The resistance of the pull-up
resistors and the capacitance of the wires should be carefully chosen.
Figure 38: DDC block diagram
C.1.1
Addresses, roles and modes
Each device connected to a DDC is identified by a unique 7-bit address (e.g. whether it’s a microcontroller,
EEPROM or D/A Converter, etc.) and can operate as either a transmitter or receiver, depending on the function
of the device. The default DDC address for u-blox GPS receivers is set to 0x42. Setting the mode field in the
CFG-PRT message for DDC accordingly can change this address.
Rp
Rp
