89
ECC (Error Correction Code or Error Checking and Correcting):
allows data
to be checked for errors during run-time. Errors can subsequently be corrected
at the same time that they’re found.
EEPROM (Electrically Erasable Programmable ROM):
also called Flash
BIOS, it is a ROM chip which can, unlike normal ROM, be updated. This allows
you to keep up with changes in the BIOS programs without having to buy a new
chip. TYAN’s BIOS updates can be found at http://www.tyan.com
ESCD (Extended System Configuration Data):
a format for storing
information about Plug-n-Play devices in the system BIOS. This information
helps properly configure the system each time it boots.
Firmware:
low-level software that controls the system hardware.
Form factor:
an industry term for the size, shape, power supply type, and
external connector type of the Personal Computer Board (PCB) or motherboard.
The standard form factors are the AT and ATX.
Global timer:
onboard hardware timer, such as the Real-Time Clock (RTC).
HDD:
stands for Hard Disk Drive, a type of fixed drive.
H-SYNC:
controls the horizontal synchronization/properties of the monitor.
HyperTransport
TM
:
a high speed, low latency, scalable point-to-point link for
interconnecting ICs on boards. It can be significantly faster than a PCI bus for
an equivalent number of pins. It provides the bandwidth and flexibility critical for
today's networking and computing platforms while retaining the fundamental
programming model of PCI.
IC (Integrated Circuit):
the formal name for the computer chip.
IDE (Integrated Device/Drive Electronics):
a simple, self-contained HDD
interface. It can handle drives up to 8.4 GB in size. Almost all IDEs sold now are
in fact Enhanced IDEs (EIDEs), with maximum capacity determined by the
hardware controller.
IDE INT (IDE Interrupt):
a hardware interrupt signal that goes to the IDE.
I/O (Input/Output):
the connection between your computer and another piece
of hardware (mouse, keyboard, etc.)
IRQ (Interrupt Request):
an electronic request that runs from a hardware
device to the CPU. The interrupt controller assigns priorities to incoming
requests and delivers them to the CPU. It is important that there is only one
device hooked up to each IRQ line; doubling up devices on IRQ lines can lock
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