User's Manual l TQMx50UC UM 0101 l © 2018 TQ-Group
Page 25
5.
SOFTWARE
5.1
System Resources
5.1.1
I2C Bus
The TQMx50UC provides a general purpose I2C port via a dedicated LPC to I2C controller in the TQ-flexiCFG block.
The following table shows the I2C address mapping for the COM Express™ I2C port.
Table 11:
I2C address mapping COM Express™ I2C port
8-bit Address
Function
Remark
0xA0
TQMx50UC EEPROM
–
0xAE
Carrier board EEPROM
Embedded EEPROM configuration not supported
5.1.2
SMBus
The TQMx50UC provides a System Management Bus (SMBus).
The following table shows the I2C address mapping for the COM Express™ SMBus port.
Table 12:
I2C address mapping COM Express™ SMBus port
8-bit Address
Function
Remark
0xA0, 0xA4
SPD EEPROMs
Only accessed by the BIOS
0x30, 0x34
Thermal Sensors
–
0x58
Hardware Monitor
–
0x64
Reserved for iRTC
–
5.1.3
Memory Map
The TQMx50UC supports the standard PC system memory and I/O memory map.
Please contact
TQ-Support
for further information about the memory map.
5.1.4
IRQ Map
The TQMx50UC supports the standard PC Interrupt routing. The integrated legacy devices (COM1, COM2) can be configured via
the BIOS to IRQ3 and IRQ4.
Please contact
TQ-Support
for further information about the Interrupt configuration.
