User's Manual l TQMaRZG2x UM 0100 l © 2021, TQ-Systems GmbH
Page 15
3.3.2.4
EEPROM
Two EEPROMs can be assembled on the TQMaRZG2x. Both EEPROMs are controlled by the IIC_DVFS bus.
•
24LC64T, 64 Kbit EEPROM (assembly option)
•
SE97BTP, combined temperature sensor and 2 Kbit EEPROM
RZ/G2x
Temp. Senor
EEPROM
24LC64T
IIC_DVFS
(AL1 / AL2)
IIC_DVFS
A1
A2
A0
EEPROM_WP
WP
Connector
EVENT_TEMPSENSOR#
SE97BTP
EEPROM
NP
3.3 V
3.3 V
1.8 V
NP
Level shifter
1.8
V ↔
3.3 V
NP
Figure 7:
Block diagram EEPROMs
3.3.2.5
EEPROM 24LC64T
The EEPROM is empty on delivery. The Write Protection signal is available at the TQMaRZG2x connectors.
Read/Write is enabled by default (100 kΩ pull-down on TQMaRZG2x).
The EEPROM has I
2
C address
3.3.2.6
EEPROM SE97BTP
The temperature sensor SE97BTP contains a 2 Kbit (256 × 8 Bit) EEPROM. For details about the temperature sensor; see 3.3.4.
The SE97BTP is controlled by the RZ/G2x I
2
C bus IIC_DVFS, device addresses see Table 22. The EEPROM is divided into two parts:
The lower 128 bytes (00h to 7Fh) can be Permanent Write Protected (PWP) or Reversible Write Protected (RWP) by software.
The upper 128 bytes (80h to FFh) are not write protected and can be used for general purpose.
The EEPROM in the SE97BTP has two I
2
C addresses:
o
EEPROM (Normal Mode):
o
EEPROM (Protected Mode):
The following table lists the parameters stored in the configuration EEPROM.
Table 10:
EEPROM, TQMaRZG2x-specific data
Offset
Payload (byte)
Padding (byte)
Size (byte)
Type
Remark
0x00
–
32
(10)
32
(10)
Binary
(Not used)
0x20
6
(10)
10
(10)
16
(10)
Binary
MAC address
0x30
8
(10)
8
(10)
16
(10)
ASCII
Serial number
0x40
Variable
Variable
64
(10)
ASCII
Order code
