TQ TQMa8MxML, Руководство пользователя

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User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 7
3.1.1.1 Pinout TQMa8MxML
The TQMa8MxML has a total of 281 LGA pads. The TQMa8MxML is soldered and thus permanently connected to the carrier board.
It is not trivial and it is not recommended to remove the TQMa8MxML.
The following table shows the TQMa8MxML pad-out, top view
through the TQMa8MxML.
Table 2: Pinout TQMa8MxML, top view through TQMa8MxML
A B C D E F G H J K L M N P R T U V W
19
ECSPI2_
SCLK
ECSPI2_
MISO
ECSPI2_
MOSI
GND
DSI_CL
K_N
DSI_CL
K_P
GND
CSI_D0
_N
CSI_D0
_P
GND
CSI_D2
_N
CSI_D2
_P
PCIE_T
XN
PCIE_T
XP
GND
USB1_
DN
USB1_
DP
19
18
ECSPI1_
MISO
ECSPI1_
MOSI
GND
DSI_D0
_N
DSI_D0
_P
GND
DSI_D2
_N
DSI_D2
_P
GND
CSI_D1
_N
CSI_D1
_P
GND
CSI_D3
_N
CSI_D3
_P
PCIE_R
XN
PCIE_R
XP
GND
USB2_
DN
USB2_
DP
18
17
ECSPI1_
SCLK
GND
ECSPI2_
SS0
GND
DSI_D1
_N
DSI_D1
_P
GND
DSI_D3
_N
DSI_D3
_P
GND
CSI_CL
K_N
CSI_CL
K_P
GND
USB2_I
D
USB2_V
BUS
PCIE_R
EF_CLK
N
PCIE_R
EF_CLK
P
GND
CLK1_O
UT
17
16
GND
ECSPI1_
SS0
GND
UART1_
TXD
UART1_
RXD
UART2_
TXD
UART2_
RXD
UART3_
TXD
UART3_
RXD
UART4_
TXD
UART4_
RXD
GND
USB1_I
D
USB1_V
BUS
GND
JTAG_T
RST#
JTAG_T
DI
CLK2_O
UT
CLK1_I
N
16
15
V_ECSP
I
V_UAR
T
GND
V_LICEL
L
GND
ISO_78
16_CLK
GND
JTAG_T
DO
JTAG_T
MS
GND
CLK2_I
N
15
14
GND
SAI3_T
XD
I2C4_S
CL
GND
RTC_EV
ENT#
ISO_78
16_IO1 JTAG_T
CK
GND
GPIO2_I
O10
GND
14
13
SAI3_T
XC
SAI3_T
XFS
I2C3_S
CL
I2C4_S
DA
GND
ISO_78
16_IO2
GND
GPIO2_I
O02
GPIO2_I
O09
GPIO2_I
O07
13
12
SAI3_M
CLK
SAI3_R
XD
I2C3_S
DA
GND
TEMP_E
VENT#
ISO_78
16_RST GPIO3_I
O14
QSPI_A
_SCLK
GND V_ENET
12
11
GND
SAI3_R
XFS
GND
I2C2_S
CL
TEST_M
ODE
GND
GPIO2_I
O00
GND
GPIO2_I
O11
GND
11
10
SAI3_R
XC
GND
I2C1_S
CL
I2C2_S
DA
GND
BOOT_
MODE1
GND
QSPI_A
_SS0#
QSPI_A
_DATA
0
GPIO2_I
O08
10
9
SAI5_R
XD0
SAI5_R
XD1
I2C1_S
DA
GND
SPDIF_
TX
BOOT_
MODE0
GPIO2_I
O01
QSPI_A
_DATA
1
QSPI_A
_DATA
2
QSPI_A
_DATA
3
9
8
GND
SAI5_R
XD2
GND
SPDIF_
EXT_CL
K
GND
SPDIF_
RX
GND
GPIO2_I
O06
GPIO2_I
O05
GPIO2_I
O04
GPIO2_I
O03
8
7
SAI5_M
CLK
GND
SAI5_R
XFS
GND
RESET_I
N#
RESET_
OUT#
ONOFF GND GND
SD2_RS
T#
GND GND GND
7
6
SAI5_R
XC
SAI5_R
XD3
GND GND
PMIC_R
ST#
V_3V3_S
D
USB2_
OTG_O
C
USB1_
OTG_O
C
USB2_
OTG_ID
PMIC_
WDOG#
GND
GPIO1_I
O06
GPIO1_I
O01
GPIO1_I
O00
SD2_W
P
GND
ENET_
MDIO
ENET_
MDC
ENET_R
D3
6
5
GND GND GND GND GND GND
USB2_
OTG_P
WR
USB1_
OTG_P
WR
USB1_
OTG_ID
M4_NM
I
GPIO1_I
O09
GPIO1_I
O07
GPIO1_I
O03
SD2_C
D#
GND
SD2_C
MD
SD2_CL
K
GND
ENET_R
D2
5
4
V_5V_I
N
V_5V_I
N
V_5V_I
N
GND GND GND
SAI1_R
XFS
SAI1_R
XD4
GND
SAI1_R
XD7
SAI1_T
XFS
GND
SAI1_T
XD5
SAI1_T
XD6
SD2_D
ATA3
SD2_D
ATA1
GND
ENET_R
D1
GND
4
3
V_5V_I
N
V_5V_I
N
V_5V_I
N
GND GND GND GND
SAI1_R
XD3
SAI1_R
XD6
GND
SAI1_T
XD1
SAI1_T
XD3
GND
SAI1_T
XD7
SD2_D
ATA2
GND
SD2_D
ATA0
ENET_R
D0
ENET_R
XC
3
2
V_5V_I
N
GND
SAI2_R
XD
SAI2_R
XFS
GND
SAI2_T
XFS
SAI1_R
XD1
GND
SAI1_R
XD5
SAI1_T
XC
GND
SAI1_T
XD2
SAI1_T
XD4
GND
ENET_T
X_CTL
ENET_T
D3
ENET_T
D1
GND
ENET_R
X_CTL
2
1
SAI2_R
XC
SAI2_M
CLK
SAI2_T
XC
SAI2_T
XD
SAI1_R
XC
SAI1_R
XD0
SAI1_R
XD2
GND
SAI1_M
CLK
SAI1_T
XD0
GND V_1V8 V_3V3 GND
ENET_T
XC
ENET_T
D2
ENET_T
D0
1
A B C D E F G H J K L M N P R T U V W