User's Manual l TQMLS10xxA UM 0105 l © 2022, TQ-Systems GmbH
Page 14
4.9
Memory
4.9.1
DDR4 SDRAM
Depending on the CPU derivative, the TQMLS10xxA supports up to 8 Gbyte DDR4 SDRAM.
ECC is optionally available and is assembled as an additional DDR4 SDRAM component.
4.9.2
SPI NOR flash
Up to two QSPI NOR flash devices can be assembled on the TQMLS10xxA.
4.9.3
EEPROM, 24LC256
A 24LC256 series EEPROM with 256 Kbit (32 kB × 8 bit) is assembled on the TQMLS10xxA.
Write Protection can be controlled by
•
CPLD
•
Board Controller
•
USRGPIO pin
A 4.7 kΩ Pull-Down is assembled on the TQMLS10xxA, thus write access is permitted.
Write protection is controlled by the CPLD. Write_Protect# of the EEPROM is not connected directly to the TQMLS10xxA
connectors, but can be controlled indirectly via USR_GPIO_1.
EEPROM
Write_Protect#
I²C bus
LS10xxA
Board
Controller
CPLD
USRGPIO_1
TQMLS10xxA
connector
Figure 11: Block diagram 24LC256 EEPROM interface
4.9.4
eMMC
The LS10xxA derivatives provide only one SDHC controller. Therefore the SD card interface cannot be used when an eMMC is
assembled on the TQMLS10xxA. Hence the SDHC interface is routed to the TQMLS10xxA connectors and can be enabled with
the SDHC_EXT_SEL control signal. A Pull-Down on the TQMLS10xxA activates the eMMC on the TQMLS10xxA by default.
Table 6:
SDHC_EXT_SEL options
SDHC_EXT_SEL
Configuration
High
External SDHC
Low
On-board eMMC
