User's Manual l TQMLS10xxA UM 0105 l © 2022, TQ-Systems GmbH
Page 8
4.1.2
LS10xxA variants, details
The following table shows the features provided by the different variants.
Fields with a red background indicate differences; fields with a green background indicate compatibility.
Table 2:
LS10xxA variants
Feature
LS1043A
LS1046A
LS1088A
Cores
Number of cores
4 × A53 Cortex
®
v8
4 × A72 Cortex
®
v8
8 × A53 Cortex
®
v8
Bus width
64-bit
64-bit
64-bit
Max. frequency (MHz)
up to 1600
up to 1800
up to 1600
Memory Size
L1 cache
32 kB I/D
32 kB D cache/ 48 kB I Cache
32 kB I/D
L2 cache
Shared 1 MB
Shared 2 MB
Shared 2 × 1 MB
Main memory type
1 × DDR3L/4, 1600 MT/s
1 × DDR4, 2100 MT/s
1 × DDR4, 2100 MT/s
Max. memory size
1 TB (40-bit address)
1 TB (40-bit address)
1 TB (40-bit address)
Interconnect
CCI 400
400 MHz
600 MHz
700 MHz
I/O
Ethernet controllers
1 × 10 Gbit/s XFI;
1 × QSGMII;
4 × 1 Gbit/s SGMII;
2 × 2.5 Gbit/s SGMII
2 × RGMII
2 × 10 Gbit/s XFI;
1 × QSGMII;
5 × 1 Gbit/s SGMII;
3 × 2.5 Gbit/s SGMII
2 × RGMII
2 × 10 Gbit/s XFI;
2 × QSGMII;
4 × 1 Gbit/s SGMII;
2 × 2.5 Gbit/s SGMII
2 × RGMII
SerDes lanes
4 lanes at up to 10 GHz
8 lanes at up to 10 GHz
8 lanes at up to 10 GHz
PCI Express controllers
3 × Gen 2.0 controllers; 5 Gbit/s
Root complex supported,
×4, ×2, and ×1 link widths
3 × Gen 3.0 controllers; 8 Gbit/s
Root complex or end point supported,
×4, ×2, and ×1 link widths
3 × Gen 3.0 controllers; 8 Gbit/s
Root complex or end point supported,
×4, ×2, and ×1 link widths
SATA
1 × SATA controller
up to 6.0 Gbit/s
1 × SATA controller
up to 6.0 Gbit/s
1 × SATA controller
up to 6.0 Gbit/s
USB
3 × USB 3.0 controllers; 5 Gbit/s
3 × USB 3.0 controllers; 5 Gbit/s
2 × USB 3.0 controllers; 5 Gbit/s
QE
HDLC, Transparent UART, TDM/SI
Not supported
HDLC, Transparent UART, TDM/SI
Integrated Flash Controller
(IFC)
8-/16-bit data width,
28-bit address width
8-/16-bit data width,
28-bit address width
8-/16-bit data width,
28-bit address width
Other peripherals
1 × eSDHC; 1 × QSPI; 1 × SPI;
4 × I
2
C; 2 × DUART; 6 × LPUART;
8 × FlexTimer
1 × eSDHC; 1 × QSPI; 1 × SPI;
4 × I
2
C; 2 × DUART; 6 × LPUART;
8 × FlexTimer
1 × eSDHC; 1 × QSPI; 1 × SPI;
4 × I
2
C; 2 × DUART;
4 × FlexTimer
Clocking
Single source clocking
DIFF_SYSCLK/
DIFF_SYSCLK_B with LVDS receiver
DIFF_SYSCLK/
DIFF_SYSCLK_B with LVDS receiver
DIFF_SYSCLK/
DIFF_SYSCLK_B with HCSL receiver
Package
Package
23 mm × 23 mm, 0.8 mm pitch,
780-pin FC-PBGA Unlidded
23 mm × 23 mm, 0.8 mm pitch,
780-pin FC-PBGA Unlidded
23 mm × 23 mm, 0.8 mm pitch,
780-pin FC-PBGA Lidded
