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User's Manual l TQMLS10xxA UM 0105 l © 2022, TQ-Systems GmbH

Page 19

Pinout TQMLS10xxA connectors (continued)

Table 9:

Pinout connector X2

CPU ball

Dir.

Level

Group

Signal

Pin

Signal

Group

Level

Dir.

CPU ball

0 V

Ground

DGND

1

2

DGND

Ground

0 V

F11

I

1.8 V (6)

IRQ

IRQ0

3

4

IRQ2

IRQ

1.8 V (6)

I

H7

F15

I

1.8 V (6)

IRQ

IRQ1

5

6

IRQ11

IRQ

1.8 / 2.5 V (7)

I/O

W3

0 V

Ground

DGND

7

8

DGND

Ground

0 V

M5

I/O

1.8 / 3.3 V (8)

IRQ

FTM3_CH4

9

10

FTM3_CH0

IRQ

1.8 / 3.3 V (8)

I/O

J4

N5

I/O

1.8 / 3.3 V (8)

IRQ

FTM3_CH5

11

12

FTM3_CH1

IRQ

1.8 / 3.3 V (8)

I/O

J5

P4

I/O

1.8 / 3.3 V (8)

IRQ

FTM3_CH6

13

14

FTM3_CH2

IRQ

1.8 / 3.3 V (8)

I/O

K5

J3

I/O

1.8 / 3.3 V (8)

IRQ

FTM3_CH7

15

16

FTM3_CH3

IRQ

1.8 / 3.3 V (8)

I/O

L5

F5

I

–

USB

USB1_ID

17

18

DGND

Ground

0 V

E7

I

–

USB

USB1_VBUS

19

20

DGND

Ground

0 V

0 V

Ground

DGND

21

22

USB1_TX_P

USB

–

O

F1

0 V

Ground

DGND

23

24

USB1_TX_M

USB

–

O

F2

F6

I/O

–

USB

USB1_D_P

25

26

DGND

Ground

0 V

E6

I/O

–

USB

USB1_D_M

27

28

DGND

Ground

0 V

0 V

Ground

DGND

29

30

USB1_RX_P

USB

–

I

E3

0 V

Ground

DGND

31

32

USB1_RX_M

USB

–

I

E4

G6

I/O

1.8 / 3.3 V (8)

USB

USB_PWRFAULT

33

34

DGND

Ground

0 V

H6

I/O

1.8 / 3.3 V (8)

USB

USB_DRVBUS

35

36

DGND

Ground

0 V

0 V

Ground

DGND

37

38

USB2_TX_P

USB

–

O

D1

0 V

Ground

DGND

39

40

USB2_TX_M

USB

–

O

D2

D5

I/O

–

USB

USB2_ID

41

42

DGND

Ground

0 V

C7

I/O

–

USB

USB2_VBUS

43

44

DGND

Ground

0 V

0 V

Ground

DGND

45

46

USB2_RX_P

USB

–

I

C3

0 V

Ground

DGND

47

48

USB2_RX_M

USB

–

I

C4

D6

I/O

–

USB

USB2_D_P

49

50

DGND

Ground

0 V

C6

I/O

–

USB

USB2_D_M

51

52

DGND

Ground

0 V

0 V

Ground

DGND

53

54

USB3_TX_P

USB

–

O

B1

0 V

Ground

DGND

55

56

USB3_TX_M

USB

–

O

B2

B6

I/O

–

USB

USB3_D_P

57

58

DGND

Ground

0 V

A6

I/O

–

USB

USB3_D_M

59

60

DGND

Ground

0 V

0 V

Ground

DGND

61

62

USB3_RX_P

USB

–

I

A3

0 V

Ground

DGND

63

64

USB3_RX_M

USB

–

I

A4

M4

I/O

1.8 / 3.3 V (8)

USB

USB2_PWRFAULT

65

66

DGND

Ground

0 V

0 V

Ground

DGND

67

68

DGND

Ground

0 V

P3

I/O

1.8 / 3.3 V (9)

SDHC

SDHC_CLK_MOD

69

70

USB2_DRVVBUS

USB

1.8 / 3.3 V (8)

I/O

L4

0 V

Ground

DGND

71

72

USB3_VBUS

USB

–

I

A7

U3

I/O

1.8 V (6)

SDHC

SDHC_CLK_SYNC_IN

73

74

USB3_ID

USB

–

I

B5

0 V

Ground

DGND

75

76

DGND

Ground

0 V

V3

I/O

1.8 V (6)

SDHC

SDHC_CLK_SYNC_OUT

77

78

SPI_SCK

SPI

1.8 V (6)

O

U2

0 V

Ground

DGND

79

80

DGND

Ground

0 V

P1

I/O

1.8 / 3.3 V (9)

SDHC

SDHC_DAT0_MOD

81

82

SPI_PCS0

SPI

1.8 V (6)

I/O

U1

R2

I/O

1.8 / 3.3 V (9)

SDHC

SDHC_DAT1_MOD

83

84

SPI_PCS1

SPI

1.8 V (6)

I/O

R3

R1

I/O

1.8 / 3.3 V (9)

SDHC

SDHC_DAT2_MOD

85

86

SPI_PCS2

SPI

1.8 V (6)

I/O

T3

T1

I/O

1.8 / 3.3 V (9)

SDHC

SDHC_DAT3_MOD

87

88

SPI_PCS3

SPI

1.8 V (6)

I/O

V1

0 V

Ground

DGND

89

90

DGND

Ground

0 V

P2

I/O

1.8 / 3.3 V (9)

SDHC

SDHC_CMD_MOD

91

92

SPI_SIN

SPI

1.8 V (6)

I/O

U3

K3

I/O

1.8 / 3.3 V (8)

SDHC

SDHC_CD#

93

94

SPI_SOUT

SPI

1.8 V (6)

I/O

V3

L3

I/O

1.8 / 3.3 V (8)

SDHC

SDHC_WP

95

96

DGND

Ground

0 V

0 V

Ground

DGND

97

98

IIC1_SCL_MOD

I2C

3.3 V

O

N1

J1

I/O

1.8 / 3.3 V (8)

UART

UART1_CTS#

99 100

IIC1_SDA_MOD

I2C

3.3 V

I/O

M1

J2

I/O

1.8 / 3.3 V (8)

UART

UART1_RTS

101 102

IIC4_SCL

I2C

1.8 / 3.3 V (8)

I/O

M3

H2

I

1.8 / 3.3 V (8)

UART

UART1_SIN

103 104

IIC4_SDA

I2C

1.8 / 3.3 V (8)

I/O

N3

H1

O

1.8 / 3.3 V (8)

UART

UART1_SOUT (10)

105 106

DGND

Ground

0 V

0 V

Ground

DGND

107 108

EVT9#

SYSTEM

1.8 V (6)

I/O

G7

K1

I/O

1.8 / 3.3 V (8)

UART

UART2_SIN

109 110

CPU_ASLEEP

SYSTEM

1.8 V (6)

I/O

E9

L2

I/O

1.8 / 3.3 V (8)

UART

UART2_SOUT (10)

111 112

DGND

Ground

0 V

0 V

Ground

DGND

113 114

CLK_OUT

SYSTEM

1.8 V (6)

O

G16

–

O

3.3 V

SYSTEM TEMP_CRIT_MOD#

115 116

DGND

Ground

0 V

–

I

3.3 V

SYSTEM RESIN#

117 118

CPU_RTC

SYSTEM

1.8 V (6)

I/O

F17

–

O

3.3 V

SYSTEM RESET_OUT#

119 120

CLKOE

Factory Test

3.3 V

I

–

6:

OVDD

7:

LVDDIN (X1-50, 52, 54)

8.

DVDD

9:

EVDD

10:

4.7 kΩ Pull-Up on carrier board is recommended.

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Содержание STKLS10 A Series

Страница 1: ...TQMLS10xxA User s Manual TQMLS10xxA UM 0105 21 03 2022...

Страница 2: ...r up sequencing 11 4 7 4 Voltage monitoring 11 4 7 5 Power consumption 12 4 8 Reset structure 13 4 9 Memory 14 4 9 1 DDR4 SDRAM 14 4 9 2 SPI NOR flash 14 4 9 3 EEPROM 24LC256 14 4 9 4 eMMC 14 4 10 Tem...

Страница 3: ...0105 l 2022 TQ Systems GmbH Page ii 8 ENVIRONMENT PROTECTION 28 8 1 RoHS 28 8 2 WEEE 28 8 3 REACH 28 8 4 EuP 28 8 5 Battery 28 8 6 Packaging 28 8 7 Other entries 28 9 APPENDIX 29 9 1 Acronyms and def...

Страница 4: ...Block diagram LS1088A Octal Cortex A53 7 Figure 5 Block diagram RCW source selection 9 Figure 6 Block diagram JTAG interface 10 Figure 7 Wiring of JTAG_TRST and PORESET 10 Figure 8 Wiring of JTAG chai...

Страница 5: ...ected Values added Reworked Figure 9 added Information added Chapter added Footnotes added Updated Link to LS1043A Errata added 0102 29 11 2019 Petz All Table 5 4 14 2 Links updated Clarified Chapters...

Страница 6: ...demarks are rightly protected by a third party 1 3 Disclaimer TQ Systems GmbH does not guarantee that the information in this User s Manual is up to date correct complete or of good quality Nor does T...

Страница 7: ...d This symbol represents important details or aspects for working with TQ products Command A font with fixed width is used to denote commands contents file names or menu items 1 7 Handling and ESD tip...

Страница 8: ...rer s specifications of the components used for example CompactFlash cards are to be taken note of They contain if applicable additional information that must be taken note of for safe and reliable op...

Страница 9: ...or Cortex A72 cores Quad Cortex A53 or Cortex A72 cores or octal Cortex A53 cores with QorIQ technology The TQMLS10xxA extends the TQ Systems GmbH product range and offers an outstanding computing per...

Страница 10: ...xA provides the following key functions and characteristics Layerscape CPUs LS1043A LS1023A LS1046A LS1026A LS1088A Oscillators Reset structure Power supply and power sequencing Voltage supervision Ho...

Страница 11: ...NICS 4 1 LS10xxA 4 1 1 LS10xxA variants block diagrams The LS10xxA module family is available with three variants of the LS10xxA CPUs from NXP The following block diagrams illustrate the differences b...

Страница 12: ...User s Manual l TQMLS10xxA UM 0105 l 2022 TQ Systems GmbH Page 7 Figure 3 Block diagram LS1046A Quad Cortex A72 Source NXP Figure 4 Block diagram LS1088A Octal Cortex A53 Source NXP...

Страница 13: ...es at up to 10 GHz 8 lanes at up to 10 GHz PCI Express controllers 3 Gen 2 0 controllers 5 Gbit s Root complex supported 4 2 and 1 link widths 3 Gen 3 0 controllers 8 Gbit s Root complex or end point...

Страница 14: ...ource is selected with signals BOOT_CFG 1 0 Table 3 RCW source selection BOOT_CFG1 BOOT_CFG0 RCW Source Low Low QSPI NOR Flash Low High I2 C LS1088A only High Low SDHC High High eMMC BOOT_CFG 1 0 is i...

Страница 15: ...tors TRST is pulled at the same time as PORESET but can also be pulled Low using an external debugger while PORESET remains unchanged Figure 7 Wiring of JTAG_TRST and PORESET The CPLD is also in the J...

Страница 16: ...eedback voltages The TQMLS10xxA provides the respective voltages in order to enable a simple connection according to customer requirements on the carrier board The voltages generated on the TQMLS10xxA...

Страница 17: ...12 76 W 85 C U Boot memory test 6 72 W 14 2 W 15 72 W Linux 100 CPU load 8 05 W 1 15 6 W 2 18 9 W 3 Attention Destruction or malfunction TQMLS10xxA heat dissipation The TQMLS10xxA belongs to a perfor...

Страница 18: ...ectors CPLD Reset Monitor RESIN LS10xxA PORESET PORESET Board Controller RESET_OUT V26 CPLD Voltage Monitoring PGOOD SYSC_POR RESET_REQ Open Drain RESET_REQ_OUT JTAG_TRST DDR4 DDR4_RST_EN TQMLS10xxA c...

Страница 19: ...ccess is permitted Write protection is controlled by the CPLD Write_Protect of the EEPROM is not connected directly to the TQMLS10xxA connectors but can be controlled indirectly via USR_GPIO_1 EEPROM...

Страница 20: ...warning at a programmed trigger level During power up the sensor is configured to T_CRIT_LOKAL 95 C by the Board Controller This value can be overwritten by the boot loader the operating system or the...

Страница 21: ...ontroller LS CPU RTC I C Bus 32 kHz Level Shifter 3 3 V 1 8 V RTC_INT _OUT CPU_RTC CLKOUT INT Figure 14 Block diagram RTC interface The RTC has I2 C address 0x51 101 0001b The RTC is clocked with a 32...

Страница 22: ...s to temperature registers EEPROM 0x53 101 0011b R W access in Normal Mode EEPROM 0x33 011 0011b R W access in Protected Mode Connected to LS10xxA accessible 24LC256 EEPROM 0x57 101 0111b STM32 Board...

Страница 23: ...VDD 59 60 DGND Ground 0 V 0 V Ground DGND 61 62 USR_GPIO_6 SYSTEM 1 8 2 5 3 3 V 4 I I 1 8 2 5 3 3 V 4 SYSTEM USR_GPIO_7 63 64 DGND Ground 0 V 3 3 V Factory Test I2C_BRD_SDA 65 66 BCTL_UARTx_TX Factory...

Страница 24: ...B3_RX_P USB I A3 0 V Ground DGND 63 64 USB3_RX_M USB I A4 M4 I O 1 8 3 3 V 8 USB USB2_PWRFAULT 65 66 DGND Ground 0 V 0 V Ground DGND 67 68 DGND Ground 0 V P3 I O 1 8 3 3 V 9 SDHC SDHC_CLK_MOD 69 70 US...

Страница 25: ...EC1_RXD3 23 24 DGND Ground 0 V 0 V Ground DGND 25 26 SWDIO Factory Test 3 3 V I O I 1 8 3 3 V 12 SYSTEM SDHC_EXT_SEL 27 28 SWCLK Factory Test 3 3 V I O O 3 3 V SYSTEM RTC_INT_OUT 29 30 DGND Ground 0...

Страница 26: ...6 SD1_TX3_P SERDES 1 35 V 18 O AD11 AH11 I 0 9 1 0 V 19 SERDES SD1_RX3_N 57 58 DGND Ground 0 V AG11 I 0 9 1 0 V 19 SERDES SD1_RX3_P 59 60 DGND Ground 0 V 0 V Ground DGND 61 62 SD2_TX0_N SERDES 1 35 V...

Страница 27: ...7 TQMLS10xxA assembly top Figure 18 TQMLS10xxA assembly bottom The labels on the TQMLS10xxA show the following information Table 12 Labels on TQMLS10xxA Label Text AK1 Serial number AK2 First MAC addr...

Страница 28: ...xxA UM 0105 l 2022 TQ Systems GmbH Page 23 5 MECHANICS 5 1 Dimensions TQMLS1043A Figure 19 TQMLS1043A dimensions side view Figure 20 TQMLS1043A dimensions top view Figure 21 TQMLS1043A dimensions top...

Страница 29: ...Systems GmbH Page 24 5 2 Dimensions TQMLS1046A TQMLS1088A Figure 22 TQMLS1046A TQMLS1088A dimensions side view Figure 23 TQMLS1046A TQMLS1088A dimensions top view Figure 24 TQMLS1046A TQMLS1088A dimen...

Страница 30: ...ors as well as the carrier board connectors while removing the TQMLS10xxA the use of the extraction tool MOZI52XX is strongly recommended See chapter 5 8 for further information Note Component placeme...

Страница 31: ...rticularly the tolerance chain PCB thickness board warpage BGA balls BGA package thermal pad heatsink as well as the maximum pressure on the LS10xxA must be taken into consideration when connecting th...

Страница 32: ...e measures always have to be implemented on the carrier board no special preventive measures were planned on the TQMLS10xxA The following measures are recommended for a carrier board Generally applica...

Страница 33: ...n the TQMLS10xxA 8 6 Packaging By environmentally friendly processes production equipment and products we contribute to the protection of our environment To be able to reuse the TQMLS10xxA it is produ...

Страница 34: ...ectromagnetic Compatibility eMMC embedded Multi Media Card ESD Electrostatic Discharge eSDHC enhanced Secure Digital High Capacity EU European Union EuP Energy using Products FC PBGA Flip Chip Plastic...

Страница 35: ...REACH Registration Evaluation Authorisation and restriction of Chemicals RF Radio Frequency RGMII Reduced Gigabit Media Independent Interface RoHS Restriction of the use of certain Hazardous Substance...

Страница 36: ...uments No Name Rev Date Company 1 Reference Manuals LS1043A LS1046A LS1088A Rev 3 02 2017 Rev 1 10 2017 Rev 0 02 2018 NXP NXP NXP 2 Data Sheets LS1043A LS1046A LS1088A Rev 3 03 2018 Rev 1 03 2018 Rev...

Страница 37: ...TQ Systems GmbH M hlstra e 2 l Gut Delling l 82229 Seefeld Info TQ Group TQ Group...

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