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User's Manual l MBLX2160A UM 0101 l © 2022, TQ-Systems GmbH
Page 26
In principle, all Ethernet interfaces have an identical structure.
•
Ethernet TI DP83867 PHY (connection via SGMII or RGMII)
•
Stacked ETH sockets with two LEDs each (green / orange)
•
10/100/1000 magnetics 749020010A
•
Individual reset signal, can be controlled via GPIO port expander
•
Individual 25 MHz reference source with quartz
The LED control can be set individually:
•
Green LED: Connected to port LED_0, Low Active control
•
Orange LED: Connected to Port LED_1, Low Active control
The PHYs have the following addresses on the MDIO bus:
Table 14:
MDIO addresses
MDIO bus
Ethernet
PHY – Ref ID
Socket
Address
EMI_1
ETH1
D27
X10-A
0001
ETH2
D29
X10-B
0010
ETH3
D31
X11-A
0011
ETH4
D32
X11-B
0100
ETH5
D28
X12-A
0101
ETH6
D34
X12-B
0110
EMI_2
ETH7
D35
X13-A
0001
ETH8
D33
X13-B
0010
ETH9
D30
X14-A
0011
ETH10
D36
X14-B
0100
ETH9 and ETH10 are connected to the CPU via RGMII. At ETH10 there is the option to use the IEEE 1588 control signals instead of
the RGMII interface. For this reason switches were installed. The two bidirectional switches are switched together via a DIP switch
(see 3.10.4).
The signals are available collected at pin header X32:
Table 15:
Pinout 20-pin header, X32
Signal
Pin
Signal
EC2_1588_TRIGIN2
1
2
SE_14443_LA
EC2_1588_PULSEO1
3
4
SE_14443_LB
EC2_1588_CLK_IN
5
6
DGND
EC2_1588_PULSEO2
7
8
SE_7816_IO1
EC2_1588_CLK_OUT
9
10
SE_7816_IO2
EC2_1588_ALARMO1
11
12
SE_7816_CLK
EC2_1588_ALARMO2
13
14
SE_7816_RST#
EC2_1588_TRIGIN1
15
16
DGND
DGND
17
18
TB_SCAN_EN#
DGND
19
20
DGND