
User's Manual l MBLS1028A UM 0100 l © 2020, TQ-Systems GmbH
Page 15
4.3.3
USB 3.0 OTG
The LS1028A has two USB3.0 controllers with integrated PHY. USB1 is used as OTG interface.
A USB 3.0 Micro B connector is assembled on the MBLS1028A.
In order to use the interface as Host/Device, a suitable adapter comes with the MBLS1028A.
Figure 14: Block diagram USB
The USB1 port of the TQMLS1028A provides a theoretical data rate of 5 Gbit/s.
Depending on the software and hardware used, the effective read and write rates of the ports may vary.
The following table shows the pinout of USB OTG connector X5.
Table 10:
Pinout USB OTG, X5
Pin
Pin name
Signal
I/O
Remark
1
VBUS
V_VBUS_USB1
P
100 µF to DGND + EMI filter
2
D–
USB1_D_M
I/O Common Mode Choke in series
3
D+
USB1_D_P
I/O Common Mode Choke in series
4
ID
USB1_ID
I
–
5
GND
DGND
P
–
6
SSTX–
USB1_TX_M
I/O Common Mode Choke in series
7
SSTX+
USB1_TX_P
I/O Common Mode Choke in series
8
GND_DRAIN
DGND
P
–
9
SSRX–
USB1_RX_M
I/O Common Mode Choke in 100 nF AC coupling capacitor
10
SSRX+
USB1_RX_P
I/O Common Mode Choke in 100 nF AC coupling capacitor
M1 … M6 Shield
DGND
P
–