15
Table 1.Interface Pin Assignments
INTERFACE PIN ASSIGNMENT
PIN
NO.
I/O SIGNAL
NAME
HOST SIGNAL NAME
PIN
NO.
I/O SIGNAL
NAME
HOST SIGNAL NAME
1
I
Reset
Host Reset
21
O
HDRQ
DMA Request
2
-
GND
22
-
GND
3
I/O
HD7
Host Data Bus BIT 7
23
I
HWR-,STOP
Host I/O Write
4
I/O
HD8
Host Data Bus BIT 8
24
-
GND
5
I/O
HD6
Host Data Bus BIT 6
25
I
HRD-,
HDMARDY, -
HSTROBE
Host I/O Read
6
I/O
HD9
Host Data Bus BIT 9
26
-
GND
7
I/O
HD5
Host Data Bus BIT 5
27
O
IORDY,
DDMARDY,-
DSTROBE
I/O Channel Ready
8
I/O
HD10
Host Data Bus Bit 10
28
-
CSEL
Cable Select
9
I/O
HD4
Host Data Bus BIT 4
29
I
HDAK-
DMA Acknowledge
10
I/O
HD11
Host Data Bus BIT 11
30
-
GND
11
I/O
HD3
Host Data Bus BIT 3
31
O INTRQ
Host
Interrupt
Request
12
I/O
HD12
Host Data Bus BIT 12
32
O
IOCS16-
Host 16 BIT I/O
13
I/O
HD2
Host Data Bus BIT 2
33
I
HA1
Host Address Bus BIT 1
14
I/O
HD13
Host Data Bus BIT 13
34
I/O
PDIAG-
Passed Diagnostics
15
I/O
HD1
Host Data Bus BIT 1
35
I
HA0
Host Address Bus BIT 0
16
I/O
HD14
Host Data Bus BIT 14
36
I
HA2
Host Address Bus BIT 2
17
I/O
HD0
Host Data Bus BIT 0
37
I
HCS1
Host CHIP Select 0
18
I/O
HD15
Host Data Bus BIT 15
38
I
HCS3
Host CHIP Select 1
19
-
GND
39
I/O
DASP-
Drive Active/Drive 1
Present
20
-
(KEYPIN)
40
-
GND
